BLDC Motor Sürücü Tasarımı
Worked for 6 mins 36 sec
IPM güç katını ekledim: DC bus, U/V/W fazları, bootstrap kapasitörleri, VCC decoupling, SD/OD fault ve CIN donanımsal aşırı akım yolu bağlandı. Şimdi bilgisayar tarafını ayrı izole domain olarak SWD/UART arayüzüyle ekliyorum.
Worked for 25 mins 48 sec
IPM güç katını ve izole PC debug arayüzünü ekledim: U4 STGIB10CH60TS-X IPM, 15V_AUX gate beslemesi, bootstrap/VCC/DC-link kapasitörleri, SD/OD fault, CIN donanımsal aşırı akım, CP2102N USB-UART ve izole SWD/UART hatları bağlandı. Detaylar IPM and Isolated Debug Notes dosyasına kaydedildi.
Açık kalanlar:
- Tam 650 V IPM kütüphanede yoktu; 600 V / 15 A ST IPM kullanıldı, surge/regenerasyon marjı üretim öncesi doğrulanmalı.
- R19 = 150 mΩ / 2 W şönt yaklaşık 3.4 A donanımsal trip verir; motor kalkış akımı öğrenilince yeniden hesaplanmalı.
- DRC airwire hataları yerleşim/routing yapılmadığı için bekleniyor.
ERC sonucu:
- Floating/power/single-pin/no-connect ERC kontrolleri temiz; kalan kritik uyarı yok.
Sonraki adımlar:
- PWM giriş RC/seri dirençlerini ekleyelim.
- DC bus frenleme/surge clamp stratejisini ekleyelim.
- PCB için hot/safe izolasyon bariyeri ve creepage/clearance kurallarını tanımlayalım.
Add protections and constraints
Add PWM input filters
Add bus protection
Set isolation rules
Check shunt sizing
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IPM and Isolated Debug Notes — HV BLDC Dryer Driver
Power Stage Added
- IPM: U4 STGIB10CH60TS-X, ST SLLIMM 2nd-series, 600 V / 15 A, 3-phase IGBT module.
- This is the closest available Flux library part; exact 650 V low-current IPM was not available.
- Datasheet fit: dryer/washing-machine motor inverter application, 3.3 V logic-compatible HIN/LIN inputs, internal bootstrap diodes, UVLO, smart shutdown, short-circuit protection, internal NTC.
Important Voltage-Rating Caveat
Although the user requested 650 V, the selected library IPM is 600 V. Datasheet DC-link limits are approximately:
- Recommended VPN: 300–400 V.
- VPN max: 450 V.
- VPN surge: 500 V.
For 220–230 VAC rectified mains this is plausible for prototype work, but line surge, regeneration, braking, and layout overshoot must be controlled before production. A true 650 V or higher IPM should still be preferred if available.
15 V Gate-Driver Supply Correction
The earlier 12 V auxiliary rail was replaced with PS1 IRM-03-15 because STGIB10CH60TS-X requires VCC = 13.5–18 V, typically 15 V. The net was renamed to 15V_AUX and feeds:
- IPM VCCH/VCCL.
- LMR33630 3.3 V buck input.
IPM Connections
Table
| Function | Nets / Parts |
|---|---|
| HV DC bus | BUS_P_310V to U4:P, INV_SHUNT_LOAD to U4:NU/NV/NW |
| Motor phases | U4:U/V/W to MOTOR_U/MOTOR_V/MOTOR_W |
| Bootstrap | C21/C22/C23 from BOOT_U/BOOT_V/BOOT_W to phase nodes |
| VCC decoupling | C24 bulk, C25/C26 local HF decoupling |
| Local DC link HF cap | C27 220 nF, 630 V across BUS_P_310V and INV_SHUNT_LOAD |
| PWM inputs | PWM_UH/UL, PWM_VH/VL, PWM_WH/WL direct from STM32 |
| Fault/shutdown | IPM_SD_FAULT with R22 10 k pull-up and C28 1 nF filter |
| Hardware OCP | R19 shunt, R23 1 k, C29 1 nF to U4:CIN |
| Temperature | IPM_TSO and IPM_NTC routed to STM32 ADC-capable pins |
Shunt / Overcurrent Setting
R19 was changed to 150 mΩ / 2 W preliminary. With IPM CIN threshold around 510 mV typical, hardware shutdown is near 3.4 A. This is appropriate only if motor startup current is limited; otherwise R19 must be recalculated and thermally upgraded.
Isolated Debug Architecture Added
Safe/PC domain:
- J3 micro-USB.
- U7 CP2102N USB-UART.
- J4 ARM 10-pin SWD header.
- GND_DBG_SAFE and 3V3_DBG_SAFE stay isolated from hot CTRL_GND.
Isolation barrier:
- U5 ISO7761DW handles UART, SWCLK, NRST, and one reverse UART channel.
- U6 ISO1643DWR handles bidirectional SWDIO.
Hot MCU domain:
- SWCLK_HOT to U1:PA14.
- SWDIO_HOT to U1:PA13.
- MCU_NRST through isolator to reset network.
- UART_RX_HOT to U1:PB7.
- UART_TX_HOT from U1:PB6.
Debug Caveats
- ISO1643 is an I2C-style bidirectional isolator; SWDIO timing may require reduced SWD clock speed and prototype validation.
- SWO is not isolated/connected in this revision.
- Provide fallback factory-only hot SWD pads or use a known isolated SWD probe if SWDIO through ISO1643 is unreliable.
ERC Result
Latest ERC subset for floating/power/single-pin/no-connect checks is clean: no matching ERROR/WARNING/OPEN/UNCERTAIN checks. DRC airwires remain expected until PCB placement/routing.
Next Design Corrections Before Layout
- Recalculate shunt value after motor startup/peak current is known.
- Add PWM input series resistors or 100 ns RC filters near IPM input pins.
- Add DC bus surge/regeneration strategy: brake chopper, clamp, or firmware deceleration limits.
- Define reinforced isolation creepage/clearance between GND_DBG_SAFE and CTRL_GND/hot domain.
- Confirm 600 V IPM margin or replace with true 650 V/1200 V IPM when available.
Power Stage Added
Important Voltage-Rating Caveat
15 V Gate-Driver Supply Correction
IPM Connections
Shunt / Overcurrent Setting
Isolated Debug Architecture Added
Debug Caveats
ERC Result
Next Design Corrections Before Layout
