Schematic for Grove Vision AI schematic

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QSPI_D0

QSPI_D2

Resistance

5.1k Ω

USR_BTN/1V8

PB2/SSPIM_DO/3V3

UD+

QSPI_D1

RX_D0_N

Terminal Type

DNP

QSPI_CLK

RX_D0_P

SEN_I2CM_SCL

QSPI_D3

GND

VBUS

Terminal Type

DNP

GND

SEN_D1/SDINSERT

Part Type

ST-TF-MR267

SEN_I2CM_SDA

PB3/SSPIM_DI/3V3

UD-

Terminal Type

DNP

UD-

GND

RX_CK_P

GND

UD+

GND

SEN_D1/SDINSERT

Resistance

5.1k Ω

Part Type

USB_C_Receptacle_USB2

GND

Net1

RX_D1_N

RX_CK_N

PB5/SSPIM_CS/3V3

GND

RX_D1_P

QSPI_CS

VCC_3V3

PB4/SSPIM_SCLK/3V3

Terminal Type

DNP

Reviews

Electrical Rule Checks

Missing Footprints

Reports parts that have no footprint.

Design Rule Checks

Overlapping Copper • 1359

Des	Net	Des	Net
D5 :K	Net 13	D8:K	Net 9
U1:SEN_D1	Net 15	U1:TX_DP1	Net 19
U1:SEN_D1	Net 15	U1:RX_CKN	Net 26
U1:SEN_D1	Net 15	U1:QSPI_DIO0	Net 28
U1:SEN_D1	Net 15	U1:SEN_I2CM_SCL	Net 34
U1:SEN_D1	Net 15	U1:SEN_I2CM_SDA	Net 35
U1:SEN_D1	Net 15	U1:SEN_PCLK	Net 38
U1:SEN_D1	Net 15	U1:SEN_D2	Net 42
U1:SEN_D1	Net 15	U1:GND5	None
U1:SEN_D1	Net 15	U1:PA0	None
U1:SEN_D1	Net 15	U1:PA3	None
U1:SEN_D1	Net 15	U1:PB3	None
U1:SEN_D1	Net 15	U1:PB10	None
U1:SEN_D1	Net 15	U1:PB11	None
U1:SEN_D1	Net 15	U1:RESETN	None
U1:SEN_D1	Net 15	U1:VDDA_DCDC	None
U1:SEN_D1	Net 15	U1:VDDA_RX	None
U1:SEN_D1	Net 15	U1:VDDIO_PIF	None
U1:SEN_D1	Net 15	U1:VX1	None
U1:TX_CKP	Net 16	U1:SEN_D1	Net 15
U1:TX_CKP	Net 16	U1:TX_CKN	Net 17
U1:TX_CKP	Net 16	U1:TX_DP1	Net 19
U1:TX_CKP	Net 16	U1:TX_DN0	Net 21
U1:TX_CKP	Net 16	U1:RX_DP0	Net 23
U1:TX_CKP	Net 16	U1:RX_DN1	Net 24
U1:TX_CKP	Net 16	U1:RX_CKN	Net 26
U1:TX_CKP	Net 16	U1:QSPI_DIO0	Net 28
U1:TX_CKP	Net 16	U1:QSPI_DIO1	Net 29
U1:TX_CKP	Net 16	U1:QSPI_CS	Net 32
U1:TX_CKP	Net 16	U1:SEN_I2CM_SCL	Net 34
U1:TX_CKP	Net 16	U1:SEN_I2CM_SDA	Net 35
U1:TX_CKP	Net 16	U1:SEN_GPIO	Net 36
U1:TX_CKP	Net 16	U1:SEN_PCLK	Net 38
U1:TX_CKP	Net 16	U1:SEN_D0	Net 41
U1:TX_CKP	Net 16	U1:SEN_D2	Net 42
U1:TX_CKP	Net 16	U1:BOOT_OPT	None
U1:TX_CKP	Net 16	U1:DCDC_OUT	None
U1:TX_CKP	Net 16	U1:GND1	None
U1:TX_CKP	Net 16	U1:GND2	None
U1:TX_CKP	Net 16	U1:GND5	None
U1:TX_CKP	Net 16	U1:GND6	None
U1:TX_CKP	Net 16	U1:PA0	None
U1:TX_CKP	Net 16	U1:PA2	None
U1:TX_CKP	Net 16	U1:PA3	None
U1:TX_CKP	Net 16	U1:PB0	None
U1:TX_CKP	Net 16	U1:PB1	None
U1:TX_CKP	Net 16	U1:PB2	None
U1:TX_CKP	Net 16	U1:PB3	None
U1:TX_CKP	Net 16	U1:PB4	None
U1:TX_CKP	Net 16	U1:PB6	None
U1:TX_CKP	Net 16	U1:PB10	None
U1:TX_CKP	Net 16	U1:PB11	None
U1:TX_CKP	Net 16	U1:RESETN	None
U1:TX_CKP	Net 16	U1:TEST_MODE	None
U1:TX_CKP	Net 16	U1:VDDA_DCDC	None
U1:TX_CKP	Net 16	U1:VDDA_RX	None
U1:TX_CKP	Net 16	U1:VDDA_TX	None
U1:TX_CKP	Net 16	U1:VDDIO_PIF	None
U1:TX_CKP	Net 16	U1:VDDIO_SIF1	None
U1:TX_CKP	Net 16	U1:VX1	None
U1:TX_CKP	Net 16	U1:XTAL_24M_O	None
U1:TX_CKN	Net 17	U1:SEN_D1	Net 15
U1:TX_CKN	Net 17	U1:TX_DP1	Net 19
U1:TX_CKN	Net 17	U1:RX_DN1	Net 24
U1:TX_CKN	Net 17	U1:RX_CKN	Net 26
U1:TX_CKN	Net 17	U1:QSPI_DIO0	Net 28
U1:TX_CKN	Net 17	U1:SEN_I2CM_SCL	Net 34
U1:TX_CKN	Net 17	U1:SEN_I2CM_SDA	Net 35
U1:TX_CKN	Net 17	U1:SEN_PCLK	Net 38
U1:TX_CKN	Net 17	U1:SEN_D0	Net 41
U1:TX_CKN	Net 17	U1:SEN_D2	Net 42
U1:TX_CKN	Net 17	U1:DCDC_OUT	None
U1:TX_CKN	Net 17	U1:GND5	None
U1:TX_CKN	Net 17	U1:PA0	None
U1:TX_CKN	Net 17	U1:PA2	None
U1:TX_CKN	Net 17	U1:PA3	None
U1:TX_CKN	Net 17	U1:PB0	None
U1:TX_CKN	Net 17	U1:PB2	None
U1:TX_CKN	Net 17	U1:PB3	None
U1:TX_CKN	Net 17	U1:PB4	None
U1:TX_CKN	Net 17	U1:PB10	None
U1:TX_CKN	Net 17	U1:PB11	None
U1:TX_CKN	Net 17	U1:RESETN	None
U1:TX_CKN	Net 17	U1:VDDA_DCDC	None
U1:TX_CKN	Net 17	U1:VDDA_RX	None
U1:TX_CKN	Net 17	U1:VDDIO_PIF	None
U1:TX_CKN	Net 17	U1:VX1	None
U1:TX_CKN	Net 17	U1:XTAL_24M_O	None
U1:TX_DN1	Net 18	U1:SEN_D1	Net 15
U1:TX_DN1	Net 18	U1:TX_CKP	Net 16
U1:TX_DN1	Net 18	U1:TX_CKN	Net 17
U1:TX_DN1	Net 18	U1:TX_DP1	Net 19
U1:TX_DN1	Net 18	U1:TX_DN0	Net 21
U1:TX_DN1	Net 18	U1:RX_DP0	Net 23
U1:TX_DN1	Net 18	U1:RX_DN1	Net 24
U1:TX_DN1	Net 18	U1:RX_CKN	Net 26
U1:TX_DN1	Net 18	U1:QSPI_DIO0	Net 28
U1:TX_DN1	Net 18	U1:QSPI_DIO1	Net 29
U1:TX_DN1	Net 18	U1:QSPI_CS	Net 32
U1:TX_DN1	Net 18	U1:SEN_I2CM_SCL	Net 34
U1:TX_DN1	Net 18	U1:SEN_I2CM_SDA	Net 35
U1:TX_DN1	Net 18	U1:SEN_GPIO	Net 36
U1:TX_DN1	Net 18	U1:SEN_PCLK	Net 38
U1:TX_DN1	Net 18	U1:SEN_D0	Net 41
U1:TX_DN1	Net 18	U1:SEN_D2	Net 42
U1:TX_DN1	Net 18	U1:BOOT_OPT	None
U1:TX_DN1	Net 18	U1:DCDC_OUT	None
U1:TX_DN1	Net 18	U1:GND1	None
U1:TX_DN1	Net 18	U1:GND2	None
U1:TX_DN1	Net 18	U1:GND5	None
U1:TX_DN1	Net 18	U1:GND6	None
U1:TX_DN1	Net 18	U1:PA0	None
U1:TX_DN1	Net 18	U1:PA2	None
U1:TX_DN1	Net 18	U1:PA3	None
U1:TX_DN1	Net 18	U1:PB0	None
U1:TX_DN1	Net 18	U1:PB1	None
U1:TX_DN1	Net 18	U1:PB2	None
U1:TX_DN1	Net 18	U1:PB3	None
U1:TX_DN1	Net 18	U1:PB4	None
U1:TX_DN1	Net 18	U1:PB6	None
U1:TX_DN1	Net 18	U1:PB10	None
U1:TX_DN1	Net 18	U1:PB11	None
U1:TX_DN1	Net 18	U1:RESETN	None
U1:TX_DN1	Net 18	U1:TEST_MODE	None
U1:TX_DN1	Net 18	U1:VDDA_DCDC	None
U1:TX_DN1	Net 18	U1:VDDA_RX	None
U1:TX_DN1	Net 18	U1:VDDA_TX	None
U1:TX_DN1	Net 18	U1:VDDIO_PIF	None
U1:TX_DN1	Net 18	U1:VDDIO_SIF1	None
U1:TX_DN1	Net 18	U1:VX1	None
U1:TX_DN1	Net 18	U1:XTAL_24M_O	None
U1:TX_DP1	Net 19	U1:QSPI_DIO0	Net 28
U1:TX_DP1	Net 19	U1:PB11	None
U1:TX_DP0	Net 20	U1:SEN_D1	Net 15
U1:TX_DP0	Net 20	U1:TX_CKP	Net 16
U1:TX_DP0	Net 20	U1:TX_CKN	Net 17
U1:TX_DP0	Net 20	U1:TX_DN1	Net 18
U1:TX_DP0	Net 20	U1:TX_DP1	Net 19
U1:TX_DP0	Net 20	U1:TX_DN0	Net 21
U1:TX_DP0	Net 20	U1:RX_DNO	Net 22
U1:TX_DP0	Net 20	U1:RX_DP0	Net 23
U1:TX_DP0	Net 20	U1:RX_DN1	Net 24
U1:TX_DP0	Net 20	U1:RX_DP1	Net 25
U1:TX_DP0	Net 20	U1:RX_CKN	Net 26
U1:TX_DP0	Net 20	U1:QSPI_DIO0	Net 28
U1:TX_DP0	Net 20	U1:QSPI_DIO1	Net 29
U1:TX_DP0	Net 20	U1:QSPI_DIO2	Net 30
U1:TX_DP0	Net 20	U1:QSPI_DIO3	Net 31
U1:TX_DP0	Net 20	U1:QSPI_CS	Net 32
U1:TX_DP0	Net 20	U1:QSPI_CLK	Net 33
U1:TX_DP0	Net 20	U1:SEN_I2CM_SCL	Net 34
U1:TX_DP0	Net 20	U1:SEN_I2CM_SDA	Net 35
U1:TX_DP0	Net 20	U1:SEN_GPIO	Net 36
U1:TX_DP0	Net 20	U1:SEN_INT	Net 37
U1:TX_DP0	Net 20	U1:SEN_PCLK	Net 38
U1:TX_DP0	Net 20	U1:SEN_XSLEEP	Net 40
U1:TX_DP0	Net 20	U1:SEN_D0	Net 41
U1:TX_DP0	Net 20	U1:SEN_D2	Net 42
U1:TX_DP0	Net 20	U1:SEN_D3	Net 43
U1:TX_DP0	Net 20	U1:BOOT_OPT	None
U1:TX_DP0	Net 20	U1:DCDC_OUT	None
U1:TX_DP0	Net 20	U1:GND1	None
U1:TX_DP0	Net 20	U1:GND2	None
U1:TX_DP0	Net 20	U1:GND5	None
U1:TX_DP0	Net 20	U1:GND6	None
U1:TX_DP0	Net 20	U1:PA0	None
U1:TX_DP0	Net 20	U1:PA2	None
U1:TX_DP0	Net 20	U1:PA3	None
U1:TX_DP0	Net 20	U1:PB0	None
U1:TX_DP0	Net 20	U1:PB1	None
U1:TX_DP0	Net 20	U1:PB2	None
U1:TX_DP0	Net 20	U1:PB3	None
U1:TX_DP0	Net 20	U1:PB4	None
U1:TX_DP0	Net 20	U1:PB5	None
U1:TX_DP0	Net 20	U1:PB6	None
U1:TX_DP0	Net 20	U1:PB7	None
U1:TX_DP0	Net 20	U1:PB8	None
U1:TX_DP0	Net 20	U1:PB9	None
U1:TX_DP0	Net 20	U1:PB10	None
U1:TX_DP0	Net 20	U1:PB11	None
U1:TX_DP0	Net 20	U1:RESETN	None
U1:TX_DP0	Net 20	U1:TEST_MODE	None
U1:TX_DP0	Net 20	U1:VDDA_DCDC	None
U1:TX_DP0	Net 20	U1:VDDA_RX	None
U1:TX_DP0	Net 20	U1:VDDA_TX	None
U1:TX_DP0	Net 20	U1:VDDIO_AON	None
U1:TX_DP0	Net 20	U1:VDDIO_PIF	None
U1:TX_DP0	Net 20	U1:VDDIO_SIF1	None
U1:TX_DP0	Net 20	U1:VDDIO_SIF2	None
U1:TX_DP0	Net 20	U1:VX1	None
U1:TX_DP0	Net 20	U1:XTAL_24M_O	None
U1:TX_DN0	Net 21	U1:SEN_D1	Net 15
U1:TX_DN0	Net 21	U1:TX_CKN	Net 17
U1:TX_DN0	Net 21	U1:TX_DP1	Net 19
U1:TX_DN0	Net 21	U1:RX_DP0	Net 23
U1:TX_DN0	Net 21	U1:RX_DN1	Net 24
U1:TX_DN0	Net 21	U1:RX_CKN	Net 26
U1:TX_DN0	Net 21	U1:QSPI_DIO0	Net 28
U1:TX_DN0	Net 21	U1:QSPI_DIO1	Net 29
U1:TX_DN0	Net 21	U1:QSPI_CS	Net 32
U1:TX_DN0	Net 21	U1:SEN_I2CM_SCL	Net 34
U1:TX_DN0	Net 21	U1:SEN_I2CM_SDA	Net 35
U1:TX_DN0	Net 21	U1:SEN_GPIO	Net 36
U1:TX_DN0	Net 21	U1:SEN_PCLK	Net 38
U1:TX_DN0	Net 21	U1:SEN_D0	Net 41
U1:TX_DN0	Net 21	U1:SEN_D2	Net 42
U1:TX_DN0	Net 21	U1:BOOT_OPT	None
U1:TX_DN0	Net 21	U1:DCDC_OUT	None
U1:TX_DN0	Net 21	U1:GND1	None
U1:TX_DN0	Net 21	U1:GND2	None
U1:TX_DN0	Net 21	U1:GND5	None
U1:TX_DN0	Net 21	U1:GND6	None
U1:TX_DN0	Net 21	U1:PA0	None
U1:TX_DN0	Net 21	U1:PA2	None
U1:TX_DN0	Net 21	U1:PA3	None
U1:TX_DN0	Net 21	U1:PB0	None
U1:TX_DN0	Net 21	U1:PB1	None
U1:TX_DN0	Net 21	U1:PB2	None
U1:TX_DN0	Net 21	U1:PB3	None
U1:TX_DN0	Net 21	U1:PB4	None
U1:TX_DN0	Net 21	U1:PB6	None
U1:TX_DN0	Net 21	U1:PB10	None
U1:TX_DN0	Net 21	U1:PB11	None
U1:TX_DN0	Net 21	U1:RESETN	None
U1:TX_DN0	Net 21	U1:TEST_MODE	None
U1:TX_DN0	Net 21	U1:VDDA_DCDC	None
U1:TX_DN0	Net 21	U1:VDDA_RX	None
U1:TX_DN0	Net 21	U1:VDDA_TX	None
U1:TX_DN0	Net 21	U1:VDDIO_PIF	None
U1:TX_DN0	Net 21	U1:VX1	None
U1:TX_DN0	Net 21	U1:XTAL_24M_O	None
U1:RX_DNO	Net 22	U1:SEN_D1	Net 15
U1:RX_DNO	Net 22	U1:TX_CKP	Net 16
U1:RX_DNO	Net 22	U1:TX_CKN	Net 17
U1:RX_DNO	Net 22	U1:TX_DN1	Net 18
U1:RX_DNO	Net 22	U1:TX_DP1	Net 19
U1:RX_DNO	Net 22	U1:TX_DN0	Net 21
U1:RX_DNO	Net 22	U1:RX_DP0	Net 23
U1:RX_DNO	Net 22	U1:RX_DN1	Net 24
U1:RX_DNO	Net 22	U1:RX_DP1	Net 25
U1:RX_DNO	Net 22	U1:RX_CKN	Net 26
U1:RX_DNO	Net 22	U1:QSPI_DIO0	Net 28
U1:RX_DNO	Net 22	U1:QSPI_DIO1	Net 29
U1:RX_DNO	Net 22	U1:QSPI_DIO3	Net 31
U1:RX_DNO	Net 22	U1:QSPI_CS	Net 32
U1:RX_DNO	Net 22	U1:SEN_I2CM_SCL	Net 34
U1:RX_DNO	Net 22	U1:SEN_I2CM_SDA	Net 35
U1:RX_DNO	Net 22	U1:SEN_GPIO	Net 36
U1:RX_DNO	Net 22	U1:SEN_INT	Net 37
U1:RX_DNO	Net 22	U1:SEN_PCLK	Net 38
U1:RX_DNO	Net 22	U1:SEN_D0	Net 41
U1:RX_DNO	Net 22	U1:SEN_D2	Net 42
U1:RX_DNO	Net 22	U1:SEN_D3	Net 43
U1:RX_DNO	Net 22	U1:BOOT_OPT	None
U1:RX_DNO	Net 22	U1:DCDC_OUT	None
U1:RX_DNO	Net 22	U1:GND1	None
U1:RX_DNO	Net 22	U1:GND2	None
U1:RX_DNO	Net 22	U1:GND5	None
U1:RX_DNO	Net 22	U1:GND6	None
U1:RX_DNO	Net 22	U1:PA0	None
U1:RX_DNO	Net 22	U1:PA2	None
U1:RX_DNO	Net 22	U1:PA3	None
U1:RX_DNO	Net 22	U1:PB0	None
U1:RX_DNO	Net 22	U1:PB1	None
U1:RX_DNO	Net 22	U1:PB2	None
U1:RX_DNO	Net 22	U1:PB3	None
U1:RX_DNO	Net 22	U1:PB4	None
U1:RX_DNO	Net 22	U1:PB6	None
U1:RX_DNO	Net 22	U1:PB7	None
U1:RX_DNO	Net 22	U1:PB8	None
U1:RX_DNO	Net 22	U1:PB9	None
U1:RX_DNO	Net 22	U1:PB10	None
U1:RX_DNO	Net 22	U1:PB11	None
U1:RX_DNO	Net 22	U1:RESETN	None
U1:RX_DNO	Net 22	U1:TEST_MODE	None
U1:RX_DNO	Net 22	U1:VDDA_DCDC	None
U1:RX_DNO	Net 22	U1:VDDA_RX	None
U1:RX_DNO	Net 22	U1:VDDA_TX	None
U1:RX_DNO	Net 22	U1:VDDIO_AON	None
U1:RX_DNO	Net 22	U1:VDDIO_PIF	None
U1:RX_DNO	Net 22	U1:VDDIO_SIF1	None
U1:RX_DNO	Net 22	U1:VDDIO_SIF2	None
U1:RX_DNO	Net 22	U1:VX1	None
U1:RX_DNO	Net 22	U1:XTAL_24M_O	None
U1:RX_DP0	Net 23	U1:SEN_D1	Net 15
U1:RX_DP0	Net 23	U1:TX_CKN	Net 17
U1:RX_DP0	Net 23	U1:TX_DP1	Net 19
U1:RX_DP0	Net 23	U1:RX_DN1	Net 24
U1:RX_DP0	Net 23	U1:RX_CKN	Net 26
U1:RX_DP0	Net 23	U1:QSPI_DIO0	Net 28
U1:RX_DP0	Net 23	U1:QSPI_CS	Net 32
U1:RX_DP0	Net 23	U1:SEN_I2CM_SCL	Net 34
U1:RX_DP0	Net 23	U1:SEN_I2CM_SDA	Net 35
U1:RX_DP0	Net 23	U1:SEN_GPIO	Net 36
U1:RX_DP0	Net 23	U1:SEN_PCLK	Net 38
U1:RX_DP0	Net 23	U1:SEN_D0	Net 41
U1:RX_DP0	Net 23	U1:SEN_D2	Net 42
U1:RX_DP0	Net 23	U1:BOOT_OPT	None
U1:RX_DP0	Net 23	U1:DCDC_OUT	None
U1:RX_DP0	Net 23	U1:GND2	None
U1:RX_DP0	Net 23	U1:GND5	None
U1:RX_DP0	Net 23	U1:GND6	None
U1:RX_DP0	Net 23	U1:PA0	None
U1:RX_DP0	Net 23	U1:PA2	None
U1:RX_DP0	Net 23	U1:PA3	None
U1:RX_DP0	Net 23	U1:PB0	None
U1:RX_DP0	Net 23	U1:PB1	None
U1:RX_DP0	Net 23	U1:PB2	None
U1:RX_DP0	Net 23	U1:PB3	None
U1:RX_DP0	Net 23	U1:PB4	None
U1:RX_DP0	Net 23	U1:PB6	None
U1:RX_DP0	Net 23	U1:PB10	None
U1:RX_DP0	Net 23	U1:PB11	None
U1:RX_DP0	Net 23	U1:RESETN	None
U1:RX_DP0	Net 23	U1:TEST_MODE	None
U1:RX_DP0	Net 23	U1:VDDA_DCDC	None
U1:RX_DP0	Net 23	U1:VDDA_RX	None
U1:RX_DP0	Net 23	U1:VDDIO_PIF	None
U1:RX_DP0	Net 23	U1:VX1	None
U1:RX_DP0	Net 23	U1:XTAL_24M_O	None
U1:RX_DN1	Net 24	U1:SEN_D1	Net 15
U1:RX_DN1	Net 24	U1:TX_DP1	Net 19
U1:RX_DN1	Net 24	U1:RX_CKN	Net 26
U1:RX_DN1	Net 24	U1:QSPI_DIO0	Net 28
U1:RX_DN1	Net 24	U1:SEN_I2CM_SCL	Net 34
U1:RX_DN1	Net 24	U1:SEN_I2CM_SDA	Net 35
U1:RX_DN1	Net 24	U1:SEN_PCLK	Net 38
U1:RX_DN1	Net 24	U1:SEN_D2	Net 42
U1:RX_DN1	Net 24	U1:DCDC_OUT	None
U1:RX_DN1	Net 24	U1:GND5	None
U1:RX_DN1	Net 24	U1:PA0	None
U1:RX_DN1	Net 24	U1:PA2	None
U1:RX_DN1	Net 24	U1:PA3	None
U1:RX_DN1	Net 24	U1:PB0	None
U1:RX_DN1	Net 24	U1:PB2	None
U1:RX_DN1	Net 24	U1:PB3	None
U1:RX_DN1	Net 24	U1:PB4	None
U1:RX_DN1	Net 24	U1:PB10	None
U1:RX_DN1	Net 24	U1:PB11	None
U1:RX_DN1	Net 24	U1:RESETN	None
U1:RX_DN1	Net 24	U1:VDDA_DCDC	None
U1:RX_DN1	Net 24	U1:VDDA_RX	None
U1:RX_DN1	Net 24	U1:VDDIO_PIF	None
U1:RX_DN1	Net 24	U1:VX1	None
U1:RX_DP1	Net 25	U1:SEN_D1	Net 15
U1:RX_DP1	Net 25	U1:TX_CKP	Net 16
U1:RX_DP1	Net 25	U1:TX_CKN	Net 17
U1:RX_DP1	Net 25	U1:TX_DN1	Net 18
U1:RX_DP1	Net 25	U1:TX_DP1	Net 19
U1:RX_DP1	Net 25	U1:TX_DN0	Net 21
U1:RX_DP1	Net 25	U1:RX_DP0	Net 23
U1:RX_DP1	Net 25	U1:RX_DN1	Net 24
U1:RX_DP1	Net 25	U1:RX_CKN	Net 26
U1:RX_DP1	Net 25	U1:QSPI_DIO0	Net 28
U1:RX_DP1	Net 25	U1:QSPI_DIO1	Net 29
U1:RX_DP1	Net 25	U1:QSPI_DIO3	Net 31
U1:RX_DP1	Net 25	U1:QSPI_CS	Net 32
U1:RX_DP1	Net 25	U1:SEN_I2CM_SCL	Net 34
U1:RX_DP1	Net 25	U1:SEN_I2CM_SDA	Net 35
U1:RX_DP1	Net 25	U1:SEN_GPIO	Net 36
U1:RX_DP1	Net 25	U1:SEN_PCLK	Net 38
U1:RX_DP1	Net 25	U1:SEN_D0	Net 41
U1:RX_DP1	Net 25	U1:SEN_D2	Net 42
U1:RX_DP1	Net 25	U1:BOOT_OPT	None
U1:RX_DP1	Net 25	U1:DCDC_OUT	None
U1:RX_DP1	Net 25	U1:GND1	None
U1:RX_DP1	Net 25	U1:GND2	None
U1:RX_DP1	Net 25	U1:GND5	None
U1:RX_DP1	Net 25	U1:GND6	None
U1:RX_DP1	Net 25	U1:PA0	None
U1:RX_DP1	Net 25	U1:PA2	None
U1:RX_DP1	Net 25	U1:PA3	None
U1:RX_DP1	Net 25	U1:PB0	None
U1:RX_DP1	Net 25	U1:PB1	None
U1:RX_DP1	Net 25	U1:PB2	None
U1:RX_DP1	Net 25	U1:PB3	None
U1:RX_DP1	Net 25	U1:PB4	None
U1:RX_DP1	Net 25	U1:PB6	None
U1:RX_DP1	Net 25	U1:PB9	None
U1:RX_DP1	Net 25	U1:PB10	None
U1:RX_DP1	Net 25	U1:PB11	None
U1:RX_DP1	Net 25	U1:RESETN	None
U1:RX_DP1	Net 25	U1:TEST_MODE	None
U1:RX_DP1	Net 25	U1:VDDA_DCDC	None
U1:RX_DP1	Net 25	U1:VDDA_RX	None
U1:RX_DP1	Net 25	U1:VDDA_TX	None
U1:RX_DP1	Net 25	U1:VDDIO_PIF	None
U1:RX_DP1	Net 25	U1:VDDIO_SIF1	None
U1:RX_DP1	Net 25	U1:VX1	None
U1:RX_DP1	Net 25	U1:XTAL_24M_O	None
U1:RX_CKN	Net 26	U1:TX_DP1	Net 19
U1:RX_CKN	Net 26	U1:QSPI_DIO0	Net 28
U1:RX_CKN	Net 26	U1:SEN_I2CM_SCL	Net 34
U1:RX_CKN	Net 26	U1:SEN_PCLK	Net 38
U1:RX_CKN	Net 26	U1:GND5	None
U1:RX_CKN	Net 26	U1:PB3	None
U1:RX_CKN	Net 26	U1:PB10	None
U1:RX_CKN	Net 26	U1:PB11	None
U1:RX_CKN	Net 26	U1:VDDA_DCDC	None
U1:QSPI_DIO1	Net 29	U1:SEN_D1	Net 15
U1:QSPI_DIO1	Net 29	U1:TX_CKN	Net 17
U1:QSPI_DIO1	Net 29	U1:TX_DP1	Net 19
U1:QSPI_DIO1	Net 29	U1:RX_DP0	Net 23
U1:QSPI_DIO1	Net 29	U1:RX_DN1	Net 24
U1:QSPI_DIO1	Net 29	U1:RX_CKN	Net 26
U1:QSPI_DIO1	Net 29	U1:QSPI_DIO0	Net 28
U1:QSPI_DIO1	Net 29	U1:QSPI_CS	Net 32
U1:QSPI_DIO1	Net 29	U1:SEN_I2CM_SCL	Net 34
U1:QSPI_DIO1	Net 29	U1:SEN_I2CM_SDA	Net 35
U1:QSPI_DIO1	Net 29	U1:SEN_GPIO	Net 36
U1:QSPI_DIO1	Net 29	U1:SEN_PCLK	Net 38
U1:QSPI_DIO1	Net 29	U1:SEN_D0	Net 41
U1:QSPI_DIO1	Net 29	U1:SEN_D2	Net 42
U1:QSPI_DIO1	Net 29	U1:BOOT_OPT	None
U1:QSPI_DIO1	Net 29	U1:DCDC_OUT	None
U1:QSPI_DIO1	Net 29	U1:GND2	None
U1:QSPI_DIO1	Net 29	U1:GND5	None
U1:QSPI_DIO1	Net 29	U1:GND6	None
U1:QSPI_DIO1	Net 29	U1:PA0	None
U1:QSPI_DIO1	Net 29	U1:PA2	None
U1:QSPI_DIO1	Net 29	U1:PA3	None
U1:QSPI_DIO1	Net 29	U1:PB0	None
U1:QSPI_DIO1	Net 29	U1:PB1	None
U1:QSPI_DIO1	Net 29	U1:PB2	None
U1:QSPI_DIO1	Net 29	U1:PB3	None
U1:QSPI_DIO1	Net 29	U1:PB4	None
U1:QSPI_DIO1	Net 29	U1:PB6	None
U1:QSPI_DIO1	Net 29	U1:PB10	None
U1:QSPI_DIO1	Net 29	U1:PB11	None
U1:QSPI_DIO1	Net 29	U1:RESETN	None
U1:QSPI_DIO1	Net 29	U1:TEST_MODE	None
U1:QSPI_DIO1	Net 29	U1:VDDA_DCDC	None
U1:QSPI_DIO1	Net 29	U1:VDDA_RX	None
U1:QSPI_DIO1	Net 29	U1:VDDIO_PIF	None
U1:QSPI_DIO1	Net 29	U1:VX1	None
U1:QSPI_DIO1	Net 29	U1:XTAL_24M_O	None
U1:QSPI_DIO2	Net 30	U1:SEN_D1	Net 15
U1:QSPI_DIO2	Net 30	U1:TX_CKP	Net 16
U1:QSPI_DIO2	Net 30	U1:TX_CKN	Net 17
U1:QSPI_DIO2	Net 30	U1:TX_DN1	Net 18
U1:QSPI_DIO2	Net 30	U1:TX_DP1	Net 19
U1:QSPI_DIO2	Net 30	U1:TX_DN0	Net 21
U1:QSPI_DIO2	Net 30	U1:RX_DNO	Net 22
U1:QSPI_DIO2	Net 30	U1:RX_DP0	Net 23
U1:QSPI_DIO2	Net 30	U1:RX_DN1	Net 24
U1:QSPI_DIO2	Net 30	U1:RX_DP1	Net 25
U1:QSPI_DIO2	Net 30	U1:RX_CKN	Net 26
U1:QSPI_DIO2	Net 30	U1:QSPI_DIO0	Net 28
U1:QSPI_DIO2	Net 30	U1:QSPI_DIO1	Net 29
U1:QSPI_DIO2	Net 30	U1:QSPI_DIO3	Net 31
U1:QSPI_DIO2	Net 30	U1:QSPI_CS	Net 32
U1:QSPI_DIO2	Net 30	U1:SEN_I2CM_SCL	Net 34
U1:QSPI_DIO2	Net 30	U1:SEN_I2CM_SDA	Net 35
U1:QSPI_DIO2	Net 30	U1:SEN_GPIO	Net 36
U1:QSPI_DIO2	Net 30	U1:SEN_INT	Net 37
U1:QSPI_DIO2	Net 30	U1:SEN_PCLK	Net 38
U1:QSPI_DIO2	Net 30	U1:SEN_D0	Net 41
U1:QSPI_DIO2	Net 30	U1:SEN_D2	Net 42
U1:QSPI_DIO2	Net 30	U1:SEN_D3	Net 43
U1:QSPI_DIO2	Net 30	U1:BOOT_OPT	None
U1:QSPI_DIO2	Net 30	U1:DCDC_OUT	None
U1:QSPI_DIO2	Net 30	U1:GND1	None
U1:QSPI_DIO2	Net 30	U1:GND2	None
U1:QSPI_DIO2	Net 30	U1:GND5	None
U1:QSPI_DIO2	Net 30	U1:GND6	None
U1:QSPI_DIO2	Net 30	U1:PA0	None
U1:QSPI_DIO2	Net 30	U1:PA2	None
U1:QSPI_DIO2	Net 30	U1:PA3	None
U1:QSPI_DIO2	Net 30	U1:PB0	None
U1:QSPI_DIO2	Net 30	U1:PB1	None
U1:QSPI_DIO2	Net 30	U1:PB2	None
U1:QSPI_DIO2	Net 30	U1:PB3	None
U1:QSPI_DIO2	Net 30	U1:PB4	None
U1:QSPI_DIO2	Net 30	U1:PB5	None
U1:QSPI_DIO2	Net 30	U1:PB6	None
U1:QSPI_DIO2	Net 30	U1:PB7	None
U1:QSPI_DIO2	Net 30	U1:PB8	None
U1:QSPI_DIO2	Net 30	U1:PB9	None
U1:QSPI_DIO2	Net 30	U1:PB10	None
U1:QSPI_DIO2	Net 30	U1:PB11	None
U1:QSPI_DIO2	Net 30	U1:RESETN	None
U1:QSPI_DIO2	Net 30	U1:TEST_MODE	None
U1:QSPI_DIO2	Net 30	U1:VDDA_DCDC	None
U1:QSPI_DIO2	Net 30	U1:VDDA_RX	None
U1:QSPI_DIO2	Net 30	U1:VDDA_TX	None
U1:QSPI_DIO2	Net 30	U1:VDDIO_AON	None
U1:QSPI_DIO2	Net 30	U1:VDDIO_PIF	None
U1:QSPI_DIO2	Net 30	U1:VDDIO_SIF1	None
U1:QSPI_DIO2	Net 30	U1:VDDIO_SIF2	None
U1:QSPI_DIO2	Net 30	U1:VX1	None
U1:QSPI_DIO2	Net 30	U1:XTAL_24M_O	None
U1:QSPI_DIO3	Net 31	U1:SEN_D1	Net 15
U1:QSPI_DIO3	Net 31	U1:TX_CKP	Net 16
U1:QSPI_DIO3	Net 31	U1:TX_CKN	Net 17
U1:QSPI_DIO3	Net 31	U1:TX_DN1	Net 18
U1:QSPI_DIO3	Net 31	U1:TX_DP1	Net 19
U1:QSPI_DIO3	Net 31	U1:TX_DN0	Net 21
U1:QSPI_DIO3	Net 31	U1:RX_DP0	Net 23
U1:QSPI_DIO3	Net 31	U1:RX_DN1	Net 24
U1:QSPI_DIO3	Net 31	U1:RX_CKN	Net 26
U1:QSPI_DIO3	Net 31	U1:QSPI_DIO0	Net 28
U1:QSPI_DIO3	Net 31	U1:QSPI_DIO1	Net 29
U1:QSPI_DIO3	Net 31	U1:QSPI_CS	Net 32
U1:QSPI_DIO3	Net 31	U1:SEN_I2CM_SCL	Net 34
U1:QSPI_DIO3	Net 31	U1:SEN_I2CM_SDA	Net 35
U1:QSPI_DIO3	Net 31	U1:SEN_GPIO	Net 36
U1:QSPI_DIO3	Net 31	U1:SEN_PCLK	Net 38
U1:QSPI_DIO3	Net 31	U1:SEN_D0	Net 41
U1:QSPI_DIO3	Net 31	U1:SEN_D2	Net 42
U1:QSPI_DIO3	Net 31	U1:BOOT_OPT	None
U1:QSPI_DIO3	Net 31	U1:DCDC_OUT	None
U1:QSPI_DIO3	Net 31	U1:GND1	None
U1:QSPI_DIO3	Net 31	U1:GND2	None
U1:QSPI_DIO3	Net 31	U1:GND5	None
U1:QSPI_DIO3	Net 31	U1:GND6	None
U1:QSPI_DIO3	Net 31	U1:PA0	None
U1:QSPI_DIO3	Net 31	U1:PA2	None
U1:QSPI_DIO3	Net 31	U1:PA3	None
U1:QSPI_DIO3	Net 31	U1:PB0	None
U1:QSPI_DIO3	Net 31	U1:PB1	None
U1:QSPI_DIO3	Net 31	U1:PB2	None
U1:QSPI_DIO3	Net 31	U1:PB3	None
U1:QSPI_DIO3	Net 31	U1:PB4	None
U1:QSPI_DIO3	Net 31	U1:PB6	None
U1:QSPI_DIO3	Net 31	U1:PB10	None
U1:QSPI_DIO3	Net 31	U1:PB11	None
U1:QSPI_DIO3	Net 31	U1:RESETN	None
U1:QSPI_DIO3	Net 31	U1:TEST_MODE	None
U1:QSPI_DIO3	Net 31	U1:VDDA_DCDC	None
U1:QSPI_DIO3	Net 31	U1:VDDA_RX	None
U1:QSPI_DIO3	Net 31	U1:VDDA_TX	None
U1:QSPI_DIO3	Net 31	U1:VDDIO_PIF	None
U1:QSPI_DIO3	Net 31	U1:VDDIO_SIF1	None
U1:QSPI_DIO3	Net 31	U1:VX1	None
U1:QSPI_DIO3	Net 31	U1:XTAL_24M_O	None
U1:QSPI_CS	Net 32	U1:SEN_D1	Net 15
U1:QSPI_CS	Net 32	U1:TX_CKN	Net 17
U1:QSPI_CS	Net 32	U1:TX_DP1	Net 19
U1:QSPI_CS	Net 32	U1:RX_DN1	Net 24
U1:QSPI_CS	Net 32	U1:RX_CKN	Net 26
U1:QSPI_CS	Net 32	U1:QSPI_DIO0	Net 28
U1:QSPI_CS	Net 32	U1:SEN_I2CM_SCL	Net 34
U1:QSPI_CS	Net 32	U1:SEN_I2CM_SDA	Net 35
U1:QSPI_CS	Net 32	U1:SEN_GPIO	Net 36
U1:QSPI_CS	Net 32	U1:SEN_PCLK	Net 38
U1:QSPI_CS	Net 32	U1:SEN_D0	Net 41
U1:QSPI_CS	Net 32	U1:SEN_D2	Net 42
U1:QSPI_CS	Net 32	U1:BOOT_OPT	None
U1:QSPI_CS	Net 32	U1:DCDC_OUT	None
U1:QSPI_CS	Net 32	U1:GND2	None
U1:QSPI_CS	Net 32	U1:GND5	None
U1:QSPI_CS	Net 32	U1:GND6	None
U1:QSPI_CS	Net 32	U1:PA0	None
U1:QSPI_CS	Net 32	U1:PA2	None
U1:QSPI_CS	Net 32	U1:PA3	None
U1:QSPI_CS	Net 32	U1:PB0	None
U1:QSPI_CS	Net 32	U1:PB1	None
U1:QSPI_CS	Net 32	U1:PB2	None
U1:QSPI_CS	Net 32	U1:PB3	None
U1:QSPI_CS	Net 32	U1:PB4	None
U1:QSPI_CS	Net 32	U1:PB6	None
U1:QSPI_CS	Net 32	U1:PB10	None
U1:QSPI_CS	Net 32	U1:PB11	None
U1:QSPI_CS	Net 32	U1:RESETN	None
U1:QSPI_CS	Net 32	U1:TEST_MODE	None
U1:QSPI_CS	Net 32	U1:VDDA_DCDC	None
U1:QSPI_CS	Net 32	U1:VDDA_RX	None
U1:QSPI_CS	Net 32	U1:VDDIO_PIF	None
U1:QSPI_CS	Net 32	U1:VX1	None
U1:QSPI_CS	Net 32	U1:XTAL_24M_O	None
U1:QSPI_CLK	Net 33	U1:SEN_D1	Net 15
U1:QSPI_CLK	Net 33	U1:TX_CKP	Net 16
U1:QSPI_CLK	Net 33	U1:TX_CKN	Net 17
U1:QSPI_CLK	Net 33	U1:TX_DN1	Net 18
U1:QSPI_CLK	Net 33	U1:TX_DP1	Net 19
U1:QSPI_CLK	Net 33	U1:TX_DN0	Net 21
U1:QSPI_CLK	Net 33	U1:RX_DNO	Net 22
U1:QSPI_CLK	Net 33	U1:RX_DP0	Net 23
U1:QSPI_CLK	Net 33	U1:RX_DN1	Net 24
U1:QSPI_CLK	Net 33	U1:RX_DP1	Net 25
U1:QSPI_CLK	Net 33	U1:RX_CKN	Net 26
U1:QSPI_CLK	Net 33	U1:QSPI_DIO0	Net 28
U1:QSPI_CLK	Net 33	U1:QSPI_DIO1	Net 29
U1:QSPI_CLK	Net 33	U1:QSPI_DIO2	Net 30
U1:QSPI_CLK	Net 33	U1:QSPI_DIO3	Net 31
U1:QSPI_CLK	Net 33	U1:QSPI_CS	Net 32
U1:QSPI_CLK	Net 33	U1:SEN_I2CM_SCL	Net 34
U1:QSPI_CLK	Net 33	U1:SEN_I2CM_SDA	Net 35
U1:QSPI_CLK	Net 33	U1:SEN_GPIO	Net 36
U1:QSPI_CLK	Net 33	U1:SEN_INT	Net 37
U1:QSPI_CLK	Net 33	U1:SEN_PCLK	Net 38
U1:QSPI_CLK	Net 33	U1:SEN_XSLEEP	Net 40
U1:QSPI_CLK	Net 33	U1:SEN_D0	Net 41
U1:QSPI_CLK	Net 33	U1:SEN_D2	Net 42
U1:QSPI_CLK	Net 33	U1:SEN_D3	Net 43
U1:QSPI_CLK	Net 33	U1:BOOT_OPT	None
U1:QSPI_CLK	Net 33	U1:DCDC_OUT	None
U1:QSPI_CLK	Net 33	U1:GND1	None
U1:QSPI_CLK	Net 33	U1:GND2	None
U1:QSPI_CLK	Net 33	U1:GND5	None
U1:QSPI_CLK	Net 33	U1:GND6	None
U1:QSPI_CLK	Net 33	U1:PA0	None
U1:QSPI_CLK	Net 33	U1:PA2	None
U1:QSPI_CLK	Net 33	U1:PA3	None
U1:QSPI_CLK	Net 33	U1:PB0	None
U1:QSPI_CLK	Net 33	U1:PB1	None
U1:QSPI_CLK	Net 33	U1:PB2	None
U1:QSPI_CLK	Net 33	U1:PB3	None
U1:QSPI_CLK	Net 33	U1:PB4	None
U1:QSPI_CLK	Net 33	U1:PB5	None
U1:QSPI_CLK	Net 33	U1:PB6	None
U1:QSPI_CLK	Net 33	U1:PB7	None
U1:QSPI_CLK	Net 33	U1:PB8	None
U1:QSPI_CLK	Net 33	U1:PB9	None
U1:QSPI_CLK	Net 33	U1:PB10	None
U1:QSPI_CLK	Net 33	U1:PB11	None
U1:QSPI_CLK	Net 33	U1:RESETN	None
U1:QSPI_CLK	Net 33	U1:TEST_MODE	None
U1:QSPI_CLK	Net 33	U1:VDDA_DCDC	None
U1:QSPI_CLK	Net 33	U1:VDDA_RX	None
U1:QSPI_CLK	Net 33	U1:VDDA_TX	None
U1:QSPI_CLK	Net 33	U1:VDDIO_AON	None
U1:QSPI_CLK	Net 33	U1:VDDIO_PIF	None
U1:QSPI_CLK	Net 33	U1:VDDIO_SIF1	None
U1:QSPI_CLK	Net 33	U1:VDDIO_SIF2	None
U1:QSPI_CLK	Net 33	U1:VX1	None
U1:QSPI_CLK	Net 33	U1:XTAL_24M_O	None
U1:SEN_I2CM_SCL	Net 34	U1:TX_DP1	Net 19
U1:SEN_I2CM_SCL	Net 34	U1:QSPI_DIO0	Net 28
U1:SEN_I2CM_SCL	Net 34	U1:PB10	None
U1:SEN_I2CM_SCL	Net 34	U1:PB11	None
U1:SEN_I2CM_SCL	Net 34	U1:VDDA_DCDC	None
U1:SEN_I2CM_SDA	Net 35	U1:TX_DP1	Net 19
U1:SEN_I2CM_SDA	Net 35	U1:RX_CKN	Net 26
U1:SEN_I2CM_SDA	Net 35	U1:QSPI_DIO0	Net 28
U1:SEN_I2CM_SDA	Net 35	U1:SEN_I2CM_SCL	Net 34
U1:SEN_I2CM_SDA	Net 35	U1:SEN_PCLK	Net 38
U1:SEN_I2CM_SDA	Net 35	U1:GND5	None
U1:SEN_I2CM_SDA	Net 35	U1:PB3	None
U1:SEN_I2CM_SDA	Net 35	U1:PB10	None
U1:SEN_I2CM_SDA	Net 35	U1:PB11	None
U1:SEN_I2CM_SDA	Net 35	U1:VDDA_DCDC	None
U1:SEN_I2CM_SDA	Net 35	U1:VDDIO_PIF	None
U1:SEN_GPIO	Net 36	U1:SEN_D1	Net 15
U1:SEN_GPIO	Net 36	U1:TX_CKN	Net 17
U1:SEN_GPIO	Net 36	U1:TX_DP1	Net 19
U1:SEN_GPIO	Net 36	U1:RX_DN1	Net 24
U1:SEN_GPIO	Net 36	U1:RX_CKN	Net 26
U1:SEN_GPIO	Net 36	U1:QSPI_DIO0	Net 28
U1:SEN_GPIO	Net 36	U1:SEN_I2CM_SCL	Net 34
U1:SEN_GPIO	Net 36	U1:SEN_I2CM_SDA	Net 35
U1:SEN_GPIO	Net 36	U1:SEN_PCLK	Net 38
U1:SEN_GPIO	Net 36	U1:SEN_D0	Net 41
U1:SEN_GPIO	Net 36	U1:SEN_D2	Net 42
U1:SEN_GPIO	Net 36	U1:BOOT_OPT	None
U1:SEN_GPIO	Net 36	U1:DCDC_OUT	None
U1:SEN_GPIO	Net 36	U1:GND2	None
U1:SEN_GPIO	Net 36	U1:GND5	None
U1:SEN_GPIO	Net 36	U1:GND6	None
U1:SEN_GPIO	Net 36	U1:PA0	None
U1:SEN_GPIO	Net 36	U1:PA2	None
U1:SEN_GPIO	Net 36	U1:PA3	None
U1:SEN_GPIO	Net 36	U1:PB0	None
U1:SEN_GPIO	Net 36	U1:PB1	None
U1:SEN_GPIO	Net 36	U1:PB2	None
U1:SEN_GPIO	Net 36	U1:PB3	None
U1:SEN_GPIO	Net 36	U1:PB4	None
U1:SEN_GPIO	Net 36	U1:PB6	None
U1:SEN_GPIO	Net 36	U1:PB10	None
U1:SEN_GPIO	Net 36	U1:PB11	None
U1:SEN_GPIO	Net 36	U1:RESETN	None
U1:SEN_GPIO	Net 36	U1:TEST_MODE	None
U1:SEN_GPIO	Net 36	U1:VDDA_DCDC	None
U1:SEN_GPIO	Net 36	U1:VDDA_RX	None
U1:SEN_GPIO	Net 36	U1:VDDIO_PIF	None
U1:SEN_GPIO	Net 36	U1:VX1	None
U1:SEN_GPIO	Net 36	U1:XTAL_24M_O	None
U1:SEN_INT	Net 37	U1:SEN_D1	Net 15
U1:SEN_INT	Net 37	U1:TX_CKP	Net 16
U1:SEN_INT	Net 37	U1:TX_CKN	Net 17
U1:SEN_INT	Net 37	U1:TX_DN1	Net 18
U1:SEN_INT	Net 37	U1:TX_DP1	Net 19
U1:SEN_INT	Net 37	U1:TX_DN0	Net 21
U1:SEN_INT	Net 37	U1:RX_DP0	Net 23
U1:SEN_INT	Net 37	U1:RX_DN1	Net 24
U1:SEN_INT	Net 37	U1:RX_DP1	Net 25
U1:SEN_INT	Net 37	U1:RX_CKN	Net 26
U1:SEN_INT	Net 37	U1:QSPI_DIO0	Net 28
U1:SEN_INT	Net 37	U1:QSPI_DIO1	Net 29
U1:SEN_INT	Net 37	U1:QSPI_DIO3	Net 31
U1:SEN_INT	Net 37	U1:QSPI_CS	Net 32
U1:SEN_INT	Net 37	U1:SEN_I2CM_SCL	Net 34
U1:SEN_INT	Net 37	U1:SEN_I2CM_SDA	Net 35
U1:SEN_INT	Net 37	U1:SEN_GPIO	Net 36
U1:SEN_INT	Net 37	U1:SEN_PCLK	Net 38
U1:SEN_INT	Net 37	U1:SEN_D0	Net 41
U1:SEN_INT	Net 37	U1:SEN_D2	Net 42
U1:SEN_INT	Net 37	U1:SEN_D3	Net 43
U1:SEN_INT	Net 37	U1:BOOT_OPT	None
U1:SEN_INT	Net 37	U1:DCDC_OUT	None
U1:SEN_INT	Net 37	U1:GND1	None
U1:SEN_INT	Net 37	U1:GND2	None
U1:SEN_INT	Net 37	U1:GND5	None
U1:SEN_INT	Net 37	U1:GND6	None
U1:SEN_INT	Net 37	U1:PA0	None
U1:SEN_INT	Net 37	U1:PA2	None
U1:SEN_INT	Net 37	U1:PA3	None
U1:SEN_INT	Net 37	U1:PB0	None
U1:SEN_INT	Net 37	U1:PB1	None
U1:SEN_INT	Net 37	U1:PB2	None
U1:SEN_INT	Net 37	U1:PB3	None
U1:SEN_INT	Net 37	U1:PB4	None
U1:SEN_INT	Net 37	U1:PB6	None
U1:SEN_INT	Net 37	U1:PB7	None
U1:SEN_INT	Net 37	U1:PB8	None
U1:SEN_INT	Net 37	U1:PB9	None
U1:SEN_INT	Net 37	U1:PB10	None
U1:SEN_INT	Net 37	U1:PB11	None
U1:SEN_INT	Net 37	U1:RESETN	None
U1:SEN_INT	Net 37	U1:TEST_MODE	None
U1:SEN_INT	Net 37	U1:VDDA_DCDC	None
U1:SEN_INT	Net 37	U1:VDDA_RX	None
U1:SEN_INT	Net 37	U1:VDDA_TX	None
U1:SEN_INT	Net 37	U1:VDDIO_AON	None
U1:SEN_INT	Net 37	U1:VDDIO_PIF	None
U1:SEN_INT	Net 37	U1:VDDIO_SIF1	None
U1:SEN_INT	Net 37	U1:VDDIO_SIF2	None
U1:SEN_INT	Net 37	U1:VX1	None
U1:SEN_INT	Net 37	U1:XTAL_24M_O	None
U1:SEN_PCLK	Net 38	U1:TX_DP1	Net 19
U1:SEN_PCLK	Net 38	U1:QSPI_DIO0	Net 28
U1:SEN_PCLK	Net 38	U1:SEN_I2CM_SCL	Net 34
U1:SEN_PCLK	Net 38	U1:GND5	None
U1:SEN_PCLK	Net 38	U1:PB3	None
U1:SEN_PCLK	Net 38	U1:PB10	None
U1:SEN_PCLK	Net 38	U1:PB11	None
U1:SEN_PCLK	Net 38	U1:VDDA_DCDC	None
U1:SEN_MCLK	Net 39	U1:SEN_D1	Net 15
U1:SEN_MCLK	Net 39	U1:TX_CKP	Net 16
U1:SEN_MCLK	Net 39	U1:TX_CKN	Net 17
U1:SEN_MCLK	Net 39	U1:TX_DN1	Net 18
U1:SEN_MCLK	Net 39	U1:TX_DP1	Net 19
U1:SEN_MCLK	Net 39	U1:TX_DP0	Net 20
U1:SEN_MCLK	Net 39	U1:TX_DN0	Net 21
U1:SEN_MCLK	Net 39	U1:RX_DNO	Net 22
U1:SEN_MCLK	Net 39	U1:RX_DP0	Net 23
U1:SEN_MCLK	Net 39	U1:RX_DN1	Net 24
U1:SEN_MCLK	Net 39	U1:RX_DP1	Net 25
U1:SEN_MCLK	Net 39	U1:RX_CKN	Net 26
U1:SEN_MCLK	Net 39	U1:QSPI_DIO0	Net 28
U1:SEN_MCLK	Net 39	U1:QSPI_DIO1	Net 29
U1:SEN_MCLK	Net 39	U1:QSPI_DIO2	Net 30
U1:SEN_MCLK	Net 39	U1:QSPI_DIO3	Net 31
U1:SEN_MCLK	Net 39	U1:QSPI_CS	Net 32
U1:SEN_MCLK	Net 39	U1:QSPI_CLK	Net 33
U1:SEN_MCLK	Net 39	U1:SEN_I2CM_SCL	Net 34
U1:SEN_MCLK	Net 39	U1:SEN_I2CM_SDA	Net 35
U1:SEN_MCLK	Net 39	U1:SEN_GPIO	Net 36
U1:SEN_MCLK	Net 39	U1:SEN_INT	Net 37
U1:SEN_MCLK	Net 39	U1:SEN_PCLK	Net 38
U1:SEN_MCLK	Net 39	U1:SEN_XSLEEP	Net 40
U1:SEN_MCLK	Net 39	U1:SEN_D0	Net 41
U1:SEN_MCLK	Net 39	U1:SEN_D2	Net 42
U1:SEN_MCLK	Net 39	U1:SEN_D3	Net 43
U1:SEN_MCLK	Net 39	U1:BOOT_OPT	None
U1:SEN_MCLK	Net 39	U1:DCDC_OUT	None
U1:SEN_MCLK	Net 39	U1:GND1	None
U1:SEN_MCLK	Net 39	U1:GND2	None
U1:SEN_MCLK	Net 39	U1:GND3	None
U1:SEN_MCLK	Net 39	U1:GND5	None
U1:SEN_MCLK	Net 39	U1:GND6	None
U1:SEN_MCLK	Net 39	U1:PA0	None
U1:SEN_MCLK	Net 39	U1:PA1	None
U1:SEN_MCLK	Net 39	U1:PA2	None
U1:SEN_MCLK	Net 39	U1:PA3	None
U1:SEN_MCLK	Net 39	U1:PB0	None
U1:SEN_MCLK	Net 39	U1:PB1	None
U1:SEN_MCLK	Net 39	U1:PB2	None
U1:SEN_MCLK	Net 39	U1:PB3	None
U1:SEN_MCLK	Net 39	U1:PB4	None
U1:SEN_MCLK	Net 39	U1:PB5	None
U1:SEN_MCLK	Net 39	U1:PB6	None
U1:SEN_MCLK	Net 39	U1:PB7	None
U1:SEN_MCLK	Net 39	U1:PB8	None
U1:SEN_MCLK	Net 39	U1:PB9	None
U1:SEN_MCLK	Net 39	U1:PB10	None
U1:SEN_MCLK	Net 39	U1:PB11	None
U1:SEN_MCLK	Net 39	U1:RESETN	None
U1:SEN_MCLK	Net 39	U1:TEST_MODE	None
U1:SEN_MCLK	Net 39	U1:VDDA_DCDC	None
U1:SEN_MCLK	Net 39	U1:VDDA_RX	None
U1:SEN_MCLK	Net 39	U1:VDDA_TX	None
U1:SEN_MCLK	Net 39	U1:VDDIO_AON	None
U1:SEN_MCLK	Net 39	U1:VDDIO_PIF	None
U1:SEN_MCLK	Net 39	U1:VDDIO_SIF1	None
U1:SEN_MCLK	Net 39	U1:VDDIO_SIF2	None
U1:SEN_MCLK	Net 39	U1:VX1	None
U1:SEN_MCLK	Net 39	U1:XTAL_24M_O	None
U1:SEN_XSLEEP	Net 40	U1:SEN_D1	Net 15
U1:SEN_XSLEEP	Net 40	U1:TX_CKP	Net 16
U1:SEN_XSLEEP	Net 40	U1:TX_CKN	Net 17
U1:SEN_XSLEEP	Net 40	U1:TX_DN1	Net 18
U1:SEN_XSLEEP	Net 40	U1:TX_DP1	Net 19
U1:SEN_XSLEEP	Net 40	U1:TX_DN0	Net 21
U1:SEN_XSLEEP	Net 40	U1:RX_DNO	Net 22
U1:SEN_XSLEEP	Net 40	U1:RX_DP0	Net 23
U1:SEN_XSLEEP	Net 40	U1:RX_DN1	Net 24
U1:SEN_XSLEEP	Net 40	U1:RX_DP1	Net 25
U1:SEN_XSLEEP	Net 40	U1:RX_CKN	Net 26
U1:SEN_XSLEEP	Net 40	U1:QSPI_DIO0	Net 28
U1:SEN_XSLEEP	Net 40	U1:QSPI_DIO1	Net 29
U1:SEN_XSLEEP	Net 40	U1:QSPI_DIO2	Net 30
U1:SEN_XSLEEP	Net 40	U1:QSPI_DIO3	Net 31
U1:SEN_XSLEEP	Net 40	U1:QSPI_CS	Net 32
U1:SEN_XSLEEP	Net 40	U1:SEN_I2CM_SCL	Net 34
U1:SEN_XSLEEP	Net 40	U1:SEN_I2CM_SDA	Net 35
U1:SEN_XSLEEP	Net 40	U1:SEN_GPIO	Net 36
U1:SEN_XSLEEP	Net 40	U1:SEN_INT	Net 37
U1:SEN_XSLEEP	Net 40	U1:SEN_PCLK	Net 38
U1:SEN_XSLEEP	Net 40	U1:SEN_D0	Net 41
U1:SEN_XSLEEP	Net 40	U1:SEN_D2	Net 42
U1:SEN_XSLEEP	Net 40	U1:SEN_D3	Net 43
U1:SEN_XSLEEP	Net 40	U1:BOOT_OPT	None
U1:SEN_XSLEEP	Net 40	U1:DCDC_OUT	None
U1:SEN_XSLEEP	Net 40	U1:GND1	None
U1:SEN_XSLEEP	Net 40	U1:GND2	None
U1:SEN_XSLEEP	Net 40	U1:GND5	None
U1:SEN_XSLEEP	Net 40	U1:GND6	None
U1:SEN_XSLEEP	Net 40	U1:PA0	None
U1:SEN_XSLEEP	Net 40	U1:PA2	None
U1:SEN_XSLEEP	Net 40	U1:PA3	None
U1:SEN_XSLEEP	Net 40	U1:PB0	None
U1:SEN_XSLEEP	Net 40	U1:PB1	None
U1:SEN_XSLEEP	Net 40	U1:PB2	None
U1:SEN_XSLEEP	Net 40	U1:PB3	None
U1:SEN_XSLEEP	Net 40	U1:PB4	None
U1:SEN_XSLEEP	Net 40	U1:PB5	None
U1:SEN_XSLEEP	Net 40	U1:PB6	None
U1:SEN_XSLEEP	Net 40	U1:PB7	None
U1:SEN_XSLEEP	Net 40	U1:PB8	None
U1:SEN_XSLEEP	Net 40	U1:PB9	None
U1:SEN_XSLEEP	Net 40	U1:PB10	None
U1:SEN_XSLEEP	Net 40	U1:PB11	None
U1:SEN_XSLEEP	Net 40	U1:RESETN	None
U1:SEN_XSLEEP	Net 40	U1:TEST_MODE	None
U1:SEN_XSLEEP	Net 40	U1:VDDA_DCDC	None
U1:SEN_XSLEEP	Net 40	U1:VDDA_RX	None
U1:SEN_XSLEEP	Net 40	U1:VDDA_TX	None
U1:SEN_XSLEEP	Net 40	U1:VDDIO_AON	None
U1:SEN_XSLEEP	Net 40	U1:VDDIO_PIF	None
U1:SEN_XSLEEP	Net 40	U1:VDDIO_SIF1	None
U1:SEN_XSLEEP	Net 40	U1:VDDIO_SIF2	None
U1:SEN_XSLEEP	Net 40	U1:VX1	None
U1:SEN_XSLEEP	Net 40	U1:XTAL_24M_O	None
U1:SEN_D0	Net 41	U1:SEN_D1	Net 15
U1:SEN_D0	Net 41	U1:TX_DP1	Net 19
U1:SEN_D0	Net 41	U1:RX_DN1	Net 24
U1:SEN_D0	Net 41	U1:RX_CKN	Net 26
U1:SEN_D0	Net 41	U1:QSPI_DIO0	Net 28
U1:SEN_D0	Net 41	U1:SEN_I2CM_SCL	Net 34
U1:SEN_D0	Net 41	U1:SEN_I2CM_SDA	Net 35
U1:SEN_D0	Net 41	U1:SEN_PCLK	Net 38
U1:SEN_D0	Net 41	U1:SEN_D2	Net 42
U1:SEN_D0	Net 41	U1:DCDC_OUT	None
U1:SEN_D0	Net 41	U1:GND5	None
U1:SEN_D0	Net 41	U1:PA0	None
U1:SEN_D0	Net 41	U1:PA2	None
U1:SEN_D0	Net 41	U1:PA3	None
U1:SEN_D0	Net 41	U1:PB0	None
U1:SEN_D0	Net 41	U1:PB2	None
U1:SEN_D0	Net 41	U1:PB3	None
U1:SEN_D0	Net 41	U1:PB4	None
U1:SEN_D0	Net 41	U1:PB10	None
U1:SEN_D0	Net 41	U1:PB11	None
U1:SEN_D0	Net 41	U1:RESETN	None
U1:SEN_D0	Net 41	U1:VDDA_DCDC	None
U1:SEN_D0	Net 41	U1:VDDA_RX	None
U1:SEN_D0	Net 41	U1:VDDIO_PIF	None
U1:SEN_D0	Net 41	U1:VX1	None
U1:SEN_D2	Net 42	U1:TX_DP1	Net 19
U1:SEN_D2	Net 42	U1:RX_CKN	Net 26
U1:SEN_D2	Net 42	U1:QSPI_DIO0	Net 28
U1:SEN_D2	Net 42	U1:SEN_I2CM_SCL	Net 34
U1:SEN_D2	Net 42	U1:SEN_I2CM_SDA	Net 35
U1:SEN_D2	Net 42	U1:SEN_PCLK	Net 38
U1:SEN_D2	Net 42	U1:GND5	None
U1:SEN_D2	Net 42	U1:PA3	None
U1:SEN_D2	Net 42	U1:PB3	None
U1:SEN_D2	Net 42	U1:PB10	None
U1:SEN_D2	Net 42	U1:PB11	None
U1:SEN_D2	Net 42	U1:RESETN	None
U1:SEN_D2	Net 42	U1:VDDA_DCDC	None
U1:SEN_D2	Net 42	U1:VDDA_RX	None
U1:SEN_D2	Net 42	U1:VDDIO_PIF	None
U1:SEN_D2	Net 42	U1:VX1	None
U1:SEN_D3	Net 43	U1:SEN_D1	Net 15
U1:SEN_D3	Net 43	U1:TX_CKP	Net 16
U1:SEN_D3	Net 43	U1:TX_CKN	Net 17
U1:SEN_D3	Net 43	U1:TX_DN1	Net 18
U1:SEN_D3	Net 43	U1:TX_DP1	Net 19
U1:SEN_D3	Net 43	U1:TX_DN0	Net 21
U1:SEN_D3	Net 43	U1:RX_DP0	Net 23
U1:SEN_D3	Net 43	U1:RX_DN1	Net 24
U1:SEN_D3	Net 43	U1:RX_DP1	Net 25
U1:SEN_D3	Net 43	U1:RX_CKN	Net 26
U1:SEN_D3	Net 43	U1:QSPI_DIO0	Net 28
U1:SEN_D3	Net 43	U1:QSPI_DIO1	Net 29
U1:SEN_D3	Net 43	U1:QSPI_DIO3	Net 31
U1:SEN_D3	Net 43	U1:QSPI_CS	Net 32
U1:SEN_D3	Net 43	U1:SEN_I2CM_SCL	Net 34
U1:SEN_D3	Net 43	U1:SEN_I2CM_SDA	Net 35
U1:SEN_D3	Net 43	U1:SEN_GPIO	Net 36
U1:SEN_D3	Net 43	U1:SEN_PCLK	Net 38
U1:SEN_D3	Net 43	U1:SEN_D0	Net 41
U1:SEN_D3	Net 43	U1:SEN_D2	Net 42
U1:SEN_D3	Net 43	U1:BOOT_OPT	None
U1:SEN_D3	Net 43	U1:DCDC_OUT	None
U1:SEN_D3	Net 43	U1:GND1	None
U1:SEN_D3	Net 43	U1:GND2	None
U1:SEN_D3	Net 43	U1:GND5	None
U1:SEN_D3	Net 43	U1:GND6	None
U1:SEN_D3	Net 43	U1:PA0	None
U1:SEN_D3	Net 43	U1:PA2	None
U1:SEN_D3	Net 43	U1:PA3	None
U1:SEN_D3	Net 43	U1:PB0	None
U1:SEN_D3	Net 43	U1:PB1	None
U1:SEN_D3	Net 43	U1:PB2	None
U1:SEN_D3	Net 43	U1:PB3	None
U1:SEN_D3	Net 43	U1:PB4	None
U1:SEN_D3	Net 43	U1:PB6	None
U1:SEN_D3	Net 43	U1:PB9	None
U1:SEN_D3	Net 43	U1:PB10	None
U1:SEN_D3	Net 43	U1:PB11	None
U1:SEN_D3	Net 43	U1:RESETN	None
U1:SEN_D3	Net 43	U1:TEST_MODE	None
U1:SEN_D3	Net 43	U1:VDDA_DCDC	None
U1:SEN_D3	Net 43	U1:VDDA_RX	None
U1:SEN_D3	Net 43	U1:VDDA_TX	None
U1:SEN_D3	Net 43	U1:VDDIO_PIF	None
U1:SEN_D3	Net 43	U1:VDDIO_SIF1	None
U1:SEN_D3	Net 43	U1:VX1	None
U1:SEN_D3	Net 43	U1:XTAL_24M_O	None
U1:BOOT_OPT	None	U1:SEN_D1	Net 15
U1:BOOT_OPT	None	U1:TX_CKN	Net 17
U1:BOOT_OPT	None	U1:TX_DP1	Net 19
U1:BOOT_OPT	None	U1:RX_DN1	Net 24
U1:BOOT_OPT	None	U1:RX_CKN	Net 26
U1:BOOT_OPT	None	U1:QSPI_DIO0	Net 28
U1:BOOT_OPT	None	U1:SEN_I2CM_SCL	Net 34
U1:BOOT_OPT	None	U1:SEN_I2CM_SDA	Net 35
U1:BOOT_OPT	None	U1:SEN_PCLK	Net 38
U1:BOOT_OPT	None	U1:SEN_D0	Net 41
U1:BOOT_OPT	None	U1:SEN_D2	Net 42
U1:DCDC_OUT	None	U1:SEN_D1	Net 15
U1:DCDC_OUT	None	U1:TX_DP1	Net 19
U1:DCDC_OUT	None	U1:RX_CKN	Net 26
U1:DCDC_OUT	None	U1:QSPI_DIO0	Net 28
U1:DCDC_OUT	None	U1:SEN_I2CM_SCL	Net 34
U1:DCDC_OUT	None	U1:SEN_I2CM_SDA	Net 35
U1:DCDC_OUT	None	U1:SEN_PCLK	Net 38
U1:DCDC_OUT	None	U1:SEN_D2	Net 42
U1:GND1	None	U1:SEN_D1	Net 15
U1:GND1	None	U1:TX_CKN	Net 17
U1:GND1	None	U1:TX_DP1	Net 19
U1:GND1	None	U1:RX_DP0	Net 23
U1:GND1	None	U1:RX_DN1	Net 24
U1:GND1	None	U1:RX_CKN	Net 26
U1:GND1	None	U1:QSPI_DIO0	Net 28
U1:GND1	None	U1:QSPI_DIO1	Net 29
U1:GND1	None	U1:QSPI_CS	Net 32
U1:GND1	None	U1:SEN_I2CM_SCL	Net 34
U1:GND1	None	U1:SEN_I2CM_SDA	Net 35
U1:GND1	None	U1:SEN_GPIO	Net 36
U1:GND1	None	U1:SEN_PCLK	Net 38
U1:GND1	None	U1:SEN_D0	Net 41
U1:GND1	None	U1:SEN_D2	Net 42
U1:GND2	None	U1:SEN_D1	Net 15
U1:GND2	None	U1:TX_CKN	Net 17
U1:GND2	None	U1:TX_DP1	Net 19
U1:GND2	None	U1:RX_DN1	Net 24
U1:GND2	None	U1:RX_CKN	Net 26
U1:GND2	None	U1:QSPI_DIO0	Net 28
U1:GND2	None	U1:SEN_I2CM_SCL	Net 34
U1:GND2	None	U1:SEN_I2CM_SDA	Net 35
U1:GND2	None	U1:SEN_PCLK	Net 38
U1:GND2	None	U1:SEN_D0	Net 41
U1:GND2	None	U1:SEN_D2	Net 42
U1:GND3	None	U1:SEN_D1	Net 15
U1:GND3	None	U1:TX_CKP	Net 16
U1:GND3	None	U1:TX_CKN	Net 17
U1:GND3	None	U1:TX_DN1	Net 18
U1:GND3	None	U1:TX_DP1	Net 19
U1:GND3	None	U1:TX_DP0	Net 20
U1:GND3	None	U1:TX_DN0	Net 21
U1:GND3	None	U1:RX_DNO	Net 22
U1:GND3	None	U1:RX_DP0	Net 23
U1:GND3	None	U1:RX_DN1	Net 24
U1:GND3	None	U1:RX_DP1	Net 25
U1:GND3	None	U1:RX_CKN	Net 26
U1:GND3	None	U1:QSPI_DIO0	Net 28
U1:GND3	None	U1:QSPI_DIO1	Net 29
U1:GND3	None	U1:QSPI_DIO2	Net 30
U1:GND3	None	U1:QSPI_DIO3	Net 31
U1:GND3	None	U1:QSPI_CS	Net 32
U1:GND3	None	U1:QSPI_CLK	Net 33
U1:GND3	None	U1:SEN_I2CM_SCL	Net 34
U1:GND3	None	U1:SEN_I2CM_SDA	Net 35
U1:GND3	None	U1:SEN_GPIO	Net 36
U1:GND3	None	U1:SEN_INT	Net 37
U1:GND3	None	U1:SEN_PCLK	Net 38
U1:GND3	None	U1:SEN_XSLEEP	Net 40
U1:GND3	None	U1:SEN_D0	Net 41
U1:GND3	None	U1:SEN_D2	Net 42
U1:GND3	None	U1:SEN_D3	Net 43
U1:GND5	None	U1:TX_DP1	Net 19
U1:GND5	None	U1:QSPI_DIO0	Net 28
U1:GND5	None	U1:SEN_I2CM_SCL	Net 34
U1:GND6	None	U1:SEN_D1	Net 15
U1:GND6	None	U1:TX_CKN	Net 17
U1:GND6	None	U1:TX_DP1	Net 19
U1:GND6	None	U1:RX_DN1	Net 24
U1:GND6	None	U1:RX_CKN	Net 26
U1:GND6	None	U1:QSPI_DIO0	Net 28
U1:GND6	None	U1:SEN_I2CM_SCL	Net 34
U1:GND6	None	U1:SEN_I2CM_SDA	Net 35
U1:GND6	None	U1:SEN_PCLK	Net 38
U1:GND6	None	U1:SEN_D0	Net 41
U1:GND6	None	U1:SEN_D2	Net 42
U1:PA0	None	U1:TX_DP1	Net 19
U1:PA0	None	U1:RX_CKN	Net 26
U1:PA0	None	U1:QSPI_DIO0	Net 28
U1:PA0	None	U1:SEN_I2CM_SCL	Net 34
U1:PA0	None	U1:SEN_I2CM_SDA	Net 35
U1:PA0	None	U1:SEN_PCLK	Net 38
U1:PA0	None	U1:SEN_D2	Net 42
U1:PA1	None	U1:SEN_D1	Net 15
U1:PA1	None	U1:TX_CKP	Net 16
U1:PA1	None	U1:TX_CKN	Net 17
U1:PA1	None	U1:TX_DN1	Net 18
U1:PA1	None	U1:TX_DP1	Net 19
U1:PA1	None	U1:TX_DP0	Net 20
U1:PA1	None	U1:TX_DN0	Net 21
U1:PA1	None	U1:RX_DNO	Net 22
U1:PA1	None	U1:RX_DP0	Net 23
U1:PA1	None	U1:RX_DN1	Net 24
U1:PA1	None	U1:RX_DP1	Net 25
U1:PA1	None	U1:RX_CKN	Net 26
U1:PA1	None	U1:QSPI_DIO0	Net 28
U1:PA1	None	U1:QSPI_DIO1	Net 29
U1:PA1	None	U1:QSPI_DIO2	Net 30
U1:PA1	None	U1:QSPI_DIO3	Net 31
U1:PA1	None	U1:QSPI_CS	Net 32
U1:PA1	None	U1:QSPI_CLK	Net 33
U1:PA1	None	U1:SEN_I2CM_SCL	Net 34
U1:PA1	None	U1:SEN_I2CM_SDA	Net 35
U1:PA1	None	U1:SEN_GPIO	Net 36
U1:PA1	None	U1:SEN_INT	Net 37
U1:PA1	None	U1:SEN_PCLK	Net 38
U1:PA1	None	U1:SEN_XSLEEP	Net 40
U1:PA1	None	U1:SEN_D0	Net 41
U1:PA1	None	U1:SEN_D2	Net 42
U1:PA1	None	U1:SEN_D3	Net 43
U1:PA2	None	U1:SEN_D1	Net 15
U1:PA2	None	U1:TX_DP1	Net 19
U1:PA2	None	U1:RX_CKN	Net 26
U1:PA2	None	U1:QSPI_DIO0	Net 28
U1:PA2	None	U1:SEN_I2CM_SCL	Net 34
U1:PA2	None	U1:SEN_I2CM_SDA	Net 35
U1:PA2	None	U1:SEN_PCLK	Net 38
U1:PA2	None	U1:SEN_D2	Net 42
U1:PA3	None	U1:TX_DP1	Net 19
U1:PA3	None	U1:RX_CKN	Net 26
U1:PA3	None	U1:QSPI_DIO0	Net 28
U1:PA3	None	U1:SEN_I2CM_SCL	Net 34
U1:PA3	None	U1:SEN_I2CM_SDA	Net 35
U1:PA3	None	U1:SEN_PCLK	Net 38
U1:PB0	None	U1:SEN_D1	Net 15
U1:PB0	None	U1:TX_DP1	Net 19
U1:PB0	None	U1:RX_CKN	Net 26
U1:PB0	None	U1:QSPI_DIO0	Net 28
U1:PB0	None	U1:SEN_I2CM_SCL	Net 34
U1:PB0	None	U1:SEN_I2CM_SDA	Net 35
U1:PB0	None	U1:SEN_PCLK	Net 38
U1:PB0	None	U1:SEN_D2	Net 42
U1:PB1	None	U1:SEN_D1	Net 15
U1:PB1	None	U1:TX_CKN	Net 17
U1:PB1	None	U1:TX_DP1	Net 19
U1:PB1	None	U1:RX_DN1	Net 24
U1:PB1	None	U1:RX_CKN	Net 26
U1:PB1	None	U1:QSPI_DIO0	Net 28
U1:PB1	None	U1:SEN_I2CM_SCL	Net 34
U1:PB1	None	U1:SEN_I2CM_SDA	Net 35
U1:PB1	None	U1:SEN_PCLK	Net 38
U1:PB1	None	U1:SEN_D0	Net 41
U1:PB1	None	U1:SEN_D2	Net 42
U1:PB2	None	U1:SEN_D1	Net 15
U1:PB2	None	U1:TX_DP1	Net 19
U1:PB2	None	U1:RX_CKN	Net 26
U1:PB2	None	U1:QSPI_DIO0	Net 28
U1:PB2	None	U1:SEN_I2CM_SCL	Net 34
U1:PB2	None	U1:SEN_I2CM_SDA	Net 35
U1:PB2	None	U1:SEN_PCLK	Net 38
U1:PB2	None	U1:SEN_D2	Net 42
U1:PB3	None	U1:TX_DP1	Net 19
U1:PB3	None	U1:QSPI_DIO0	Net 28
U1:PB3	None	U1:SEN_I2CM_SCL	Net 34
U1:PB4	None	U1:SEN_D1	Net 15
U1:PB4	None	U1:TX_DP1	Net 19
U1:PB4	None	U1:RX_CKN	Net 26
U1:PB4	None	U1:QSPI_DIO0	Net 28
U1:PB4	None	U1:SEN_I2CM_SCL	Net 34
U1:PB4	None	U1:SEN_I2CM_SDA	Net 35
U1:PB4	None	U1:SEN_PCLK	Net 38
U1:PB4	None	U1:SEN_D2	Net 42
U1:PB5	None	U1:SEN_D1	Net 15
U1:PB5	None	U1:TX_CKP	Net 16
U1:PB5	None	U1:TX_CKN	Net 17
U1:PB5	None	U1:TX_DN1	Net 18
U1:PB5	None	U1:TX_DP1	Net 19
U1:PB5	None	U1:TX_DN0	Net 21
U1:PB5	None	U1:RX_DNO	Net 22
U1:PB5	None	U1:RX_DP0	Net 23
U1:PB5	None	U1:RX_DN1	Net 24
U1:PB5	None	U1:RX_DP1	Net 25
U1:PB5	None	U1:RX_CKN	Net 26
U1:PB5	None	U1:QSPI_DIO0	Net 28
U1:PB5	None	U1:QSPI_DIO1	Net 29
U1:PB5	None	U1:QSPI_DIO3	Net 31
U1:PB5	None	U1:QSPI_CS	Net 32
U1:PB5	None	U1:SEN_I2CM_SCL	Net 34
U1:PB5	None	U1:SEN_I2CM_SDA	Net 35
U1:PB5	None	U1:SEN_GPIO	Net 36
U1:PB5	None	U1:SEN_INT	Net 37
U1:PB5	None	U1:SEN_PCLK	Net 38
U1:PB5	None	U1:SEN_D0	Net 41
U1:PB5	None	U1:SEN_D2	Net 42
U1:PB5	None	U1:SEN_D3	Net 43
U1:PB6	None	U1:SEN_D1	Net 15
U1:PB6	None	U1:TX_CKN	Net 17
U1:PB6	None	U1:TX_DP1	Net 19
U1:PB6	None	U1:RX_DN1	Net 24
U1:PB6	None	U1:RX_CKN	Net 26
U1:PB6	None	U1:QSPI_DIO0	Net 28
U1:PB6	None	U1:SEN_I2CM_SCL	Net 34
U1:PB6	None	U1:SEN_I2CM_SDA	Net 35
U1:PB6	None	U1:SEN_PCLK	Net 38
U1:PB6	None	U1:SEN_D0	Net 41
U1:PB6	None	U1:SEN_D2	Net 42
U1:PB7	None	U1:SEN_D1	Net 15
U1:PB7	None	U1:TX_CKP	Net 16
U1:PB7	None	U1:TX_CKN	Net 17
U1:PB7	None	U1:TX_DN1	Net 18
U1:PB7	None	U1:TX_DP1	Net 19
U1:PB7	None	U1:TX_DN0	Net 21
U1:PB7	None	U1:RX_DP0	Net 23
U1:PB7	None	U1:RX_DN1	Net 24
U1:PB7	None	U1:RX_DP1	Net 25
U1:PB7	None	U1:RX_CKN	Net 26
U1:PB7	None	U1:QSPI_DIO0	Net 28
U1:PB7	None	U1:QSPI_DIO1	Net 29
U1:PB7	None	U1:QSPI_DIO3	Net 31
U1:PB7	None	U1:QSPI_CS	Net 32
U1:PB7	None	U1:SEN_I2CM_SCL	Net 34
U1:PB7	None	U1:SEN_I2CM_SDA	Net 35
U1:PB7	None	U1:SEN_GPIO	Net 36
U1:PB7	None	U1:SEN_PCLK	Net 38
U1:PB7	None	U1:SEN_D0	Net 41
U1:PB7	None	U1:SEN_D2	Net 42
U1:PB7	None	U1:SEN_D3	Net 43
U1:PB8	None	U1:SEN_D1	Net 15
U1:PB8	None	U1:TX_CKP	Net 16
U1:PB8	None	U1:TX_CKN	Net 17
U1:PB8	None	U1:TX_DN1	Net 18
U1:PB8	None	U1:TX_DP1	Net 19
U1:PB8	None	U1:TX_DN0	Net 21
U1:PB8	None	U1:RX_DP0	Net 23
U1:PB8	None	U1:RX_DN1	Net 24
U1:PB8	None	U1:RX_DP1	Net 25
U1:PB8	None	U1:RX_CKN	Net 26
U1:PB8	None	U1:QSPI_DIO0	Net 28
U1:PB8	None	U1:QSPI_DIO1	Net 29
U1:PB8	None	U1:QSPI_DIO3	Net 31
U1:PB8	None	U1:QSPI_CS	Net 32
U1:PB8	None	U1:SEN_I2CM_SCL	Net 34
U1:PB8	None	U1:SEN_I2CM_SDA	Net 35
U1:PB8	None	U1:SEN_GPIO	Net 36
U1:PB8	None	U1:SEN_PCLK	Net 38
U1:PB8	None	U1:SEN_D0	Net 41
U1:PB8	None	U1:SEN_D2	Net 42
U1:PB8	None	U1:SEN_D3	Net 43
U1:PB9	None	U1:SEN_D1	Net 15
U1:PB9	None	U1:TX_CKP	Net 16
U1:PB9	None	U1:TX_CKN	Net 17
U1:PB9	None	U1:TX_DN1	Net 18
U1:PB9	None	U1:TX_DP1	Net 19
U1:PB9	None	U1:TX_DN0	Net 21
U1:PB9	None	U1:RX_DP0	Net 23
U1:PB9	None	U1:RX_DN1	Net 24
U1:PB9	None	U1:RX_CKN	Net 26
U1:PB9	None	U1:QSPI_DIO0	Net 28
U1:PB9	None	U1:QSPI_DIO1	Net 29
U1:PB9	None	U1:QSPI_DIO3	Net 31
U1:PB9	None	U1:QSPI_CS	Net 32
U1:PB9	None	U1:SEN_I2CM_SCL	Net 34
U1:PB9	None	U1:SEN_I2CM_SDA	Net 35
U1:PB9	None	U1:SEN_GPIO	Net 36
U1:PB9	None	U1:SEN_PCLK	Net 38
U1:PB9	None	U1:SEN_D0	Net 41
U1:PB9	None	U1:SEN_D2	Net 42
U1:PB10	None	U1:TX_DP1	Net 19
U1:PB10	None	U1:QSPI_DIO0	Net 28
U1:PB11	None	U1:QSPI_DIO0	Net 28
U1:RESETN	None	U1:TX_DP1	Net 19
U1:RESETN	None	U1:RX_CKN	Net 26
U1:RESETN	None	U1:QSPI_DIO0	Net 28
U1:RESETN	None	U1:SEN_I2CM_SCL	Net 34
U1:RESETN	None	U1:SEN_I2CM_SDA	Net 35
U1:RESETN	None	U1:SEN_PCLK	Net 38
U1:TEST_MODE	None	U1:SEN_D1	Net 15
U1:TEST_MODE	None	U1:TX_CKN	Net 17
U1:TEST_MODE	None	U1:TX_DP1	Net 19
U1:TEST_MODE	None	U1:RX_DN1	Net 24
U1:TEST_MODE	None	U1:RX_CKN	Net 26
U1:TEST_MODE	None	U1:QSPI_DIO0	Net 28
U1:TEST_MODE	None	U1:SEN_I2CM_SCL	Net 34
U1:TEST_MODE	None	U1:SEN_I2CM_SDA	Net 35
U1:TEST_MODE	None	U1:SEN_PCLK	Net 38
U1:TEST_MODE	None	U1:SEN_D0	Net 41
U1:TEST_MODE	None	U1:SEN_D2	Net 42
U1:VDDA_DCDC	None	U1:TX_DP1	Net 19
U1:VDDA_DCDC	None	U1:QSPI_DIO0	Net 28
U1:VDDA_RX	None	U1:TX_DP1	Net 19
U1:VDDA_RX	None	U1:RX_CKN	Net 26
U1:VDDA_RX	None	U1:QSPI_DIO0	Net 28
U1:VDDA_RX	None	U1:SEN_I2CM_SCL	Net 34
U1:VDDA_RX	None	U1:SEN_I2CM_SDA	Net 35
U1:VDDA_RX	None	U1:SEN_PCLK	Net 38
U1:VDDA_TX	None	U1:SEN_D1	Net 15
U1:VDDA_TX	None	U1:TX_CKN	Net 17
U1:VDDA_TX	None	U1:TX_DP1	Net 19
U1:VDDA_TX	None	U1:RX_DP0	Net 23
U1:VDDA_TX	None	U1:RX_DN1	Net 24
U1:VDDA_TX	None	U1:RX_CKN	Net 26
U1:VDDA_TX	None	U1:QSPI_DIO0	Net 28
U1:VDDA_TX	None	U1:QSPI_DIO1	Net 29
U1:VDDA_TX	None	U1:QSPI_CS	Net 32
U1:VDDA_TX	None	U1:SEN_I2CM_SCL	Net 34
U1:VDDA_TX	None	U1:SEN_I2CM_SDA	Net 35
U1:VDDA_TX	None	U1:SEN_GPIO	Net 36
U1:VDDA_TX	None	U1:SEN_PCLK	Net 38
U1:VDDA_TX	None	U1:SEN_D0	Net 41
U1:VDDA_TX	None	U1:SEN_D2	Net 42
U1:VDDIO_AON	None	U1:SEN_D1	Net 15
U1:VDDIO_AON	None	U1:TX_CKP	Net 16
U1:VDDIO_AON	None	U1:TX_CKN	Net 17
U1:VDDIO_AON	None	U1:TX_DN1	Net 18
U1:VDDIO_AON	None	U1:TX_DP1	Net 19
U1:VDDIO_AON	None	U1:TX_DN0	Net 21
U1:VDDIO_AON	None	U1:RX_DP0	Net 23
U1:VDDIO_AON	None	U1:RX_DN1	Net 24
U1:VDDIO_AON	None	U1:RX_DP1	Net 25
U1:VDDIO_AON	None	U1:RX_CKN	Net 26
U1:VDDIO_AON	None	U1:QSPI_DIO0	Net 28
U1:VDDIO_AON	None	U1:QSPI_DIO1	Net 29
U1:VDDIO_AON	None	U1:QSPI_DIO3	Net 31
U1:VDDIO_AON	None	U1:QSPI_CS	Net 32
U1:VDDIO_AON	None	U1:SEN_I2CM_SCL	Net 34
U1:VDDIO_AON	None	U1:SEN_I2CM_SDA	Net 35
U1:VDDIO_AON	None	U1:SEN_GPIO	Net 36
U1:VDDIO_AON	None	U1:SEN_PCLK	Net 38
U1:VDDIO_AON	None	U1:SEN_D0	Net 41
U1:VDDIO_AON	None	U1:SEN_D2	Net 42
U1:VDDIO_AON	None	U1:SEN_D3	Net 43
U1:VDDIO_PIF	None	U1:TX_DP1	Net 19
U1:VDDIO_PIF	None	U1:RX_CKN	Net 26
U1:VDDIO_PIF	None	U1:QSPI_DIO0	Net 28
U1:VDDIO_PIF	None	U1:SEN_I2CM_SCL	Net 34
U1:VDDIO_PIF	None	U1:SEN_PCLK	Net 38
U1:VDDIO_SIF1	None	U1:SEN_D1	Net 15
U1:VDDIO_SIF1	None	U1:TX_CKN	Net 17
U1:VDDIO_SIF1	None	U1:TX_DP1	Net 19
U1:VDDIO_SIF1	None	U1:TX_DN0	Net 21
U1:VDDIO_SIF1	None	U1:RX_DP0	Net 23
U1:VDDIO_SIF1	None	U1:RX_DN1	Net 24
U1:VDDIO_SIF1	None	U1:RX_CKN	Net 26
U1:VDDIO_SIF1	None	U1:QSPI_DIO0	Net 28
U1:VDDIO_SIF1	None	U1:QSPI_DIO1	Net 29
U1:VDDIO_SIF1	None	U1:QSPI_CS	Net 32
U1:VDDIO_SIF1	None	U1:SEN_I2CM_SCL	Net 34
U1:VDDIO_SIF1	None	U1:SEN_I2CM_SDA	Net 35
U1:VDDIO_SIF1	None	U1:SEN_GPIO	Net 36
U1:VDDIO_SIF1	None	U1:SEN_PCLK	Net 38
U1:VDDIO_SIF1	None	U1:SEN_D0	Net 41
U1:VDDIO_SIF1	None	U1:SEN_D2	Net 42
U1:VDDIO_SIF2	None	U1:SEN_D1	Net 15
U1:VDDIO_SIF2	None	U1:TX_CKP	Net 16
U1:VDDIO_SIF2	None	U1:TX_CKN	Net 17
U1:VDDIO_SIF2	None	U1:TX_DN1	Net 18
U1:VDDIO_SIF2	None	U1:TX_DP1	Net 19
U1:VDDIO_SIF2	None	U1:TX_DN0	Net 21
U1:VDDIO_SIF2	None	U1:RX_DP0	Net 23
U1:VDDIO_SIF2	None	U1:RX_DN1	Net 24
U1:VDDIO_SIF2	None	U1:RX_DP1	Net 25
U1:VDDIO_SIF2	None	U1:RX_CKN	Net 26
U1:VDDIO_SIF2	None	U1:QSPI_DIO0	Net 28
U1:VDDIO_SIF2	None	U1:QSPI_DIO1	Net 29
U1:VDDIO_SIF2	None	U1:QSPI_DIO3	Net 31
U1:VDDIO_SIF2	None	U1:QSPI_CS	Net 32
U1:VDDIO_SIF2	None	U1:SEN_I2CM_SCL	Net 34
U1:VDDIO_SIF2	None	U1:SEN_I2CM_SDA	Net 35
U1:VDDIO_SIF2	None	U1:SEN_GPIO	Net 36
U1:VDDIO_SIF2	None	U1:SEN_PCLK	Net 38
U1:VDDIO_SIF2	None	U1:SEN_D0	Net 41
U1:VDDIO_SIF2	None	U1:SEN_D2	Net 42
U1:VDDIO_SIF2	None	U1:SEN_D3	Net 43
U1:VX1	None	U1:TX_DP1	Net 19
U1:VX1	None	U1:RX_CKN	Net 26
U1:VX1	None	U1:QSPI_DIO0	Net 28
U1:VX1	None	U1:SEN_I2CM_SCL	Net 34
U1:VX1	None	U1:SEN_I2CM_SDA	Net 35
U1:VX1	None	U1:SEN_PCLK	Net 38
U1:XTAL_24M_I	None	U1:SEN_D1	Net 15
U1:XTAL_24M_I	None	U1:TX_CKP	Net 16
U1:XTAL_24M_I	None	U1:TX_CKN	Net 17
U1:XTAL_24M_I	None	U1:TX_DN1	Net 18
U1:XTAL_24M_I	None	U1:TX_DP1	Net 19
U1:XTAL_24M_I	None	U1:TX_DP0	Net 20
U1:XTAL_24M_I	None	U1:TX_DN0	Net 21
U1:XTAL_24M_I	None	U1:RX_DNO	Net 22
U1:XTAL_24M_I	None	U1:RX_DP0	Net 23
U1:XTAL_24M_I	None	U1:RX_DN1	Net 24
U1:XTAL_24M_I	None	U1:RX_DP1	Net 25
U1:XTAL_24M_I	None	U1:RX_CKN	Net 26
U1:XTAL_24M_I	None	U1:QSPI_DIO0	Net 28
U1:XTAL_24M_I	None	U1:QSPI_DIO1	Net 29
U1:XTAL_24M_I	None	U1:QSPI_DIO2	Net 30
U1:XTAL_24M_I	None	U1:QSPI_DIO3	Net 31
U1:XTAL_24M_I	None	U1:QSPI_CS	Net 32
U1:XTAL_24M_I	None	U1:QSPI_CLK	Net 33
U1:XTAL_24M_I	None	U1:SEN_I2CM_SCL	Net 34
U1:XTAL_24M_I	None	U1:SEN_I2CM_SDA	Net 35
U1:XTAL_24M_I	None	U1:SEN_GPIO	Net 36
U1:XTAL_24M_I	None	U1:SEN_INT	Net 37
U1:XTAL_24M_I	None	U1:SEN_PCLK	Net 38
U1:XTAL_24M_I	None	U1:SEN_MCLK	Net 39
U1:XTAL_24M_I	None	U1:SEN_XSLEEP	Net 40
U1:XTAL_24M_I	None	U1:SEN_D0	Net 41
U1:XTAL_24M_I	None	U1:SEN_D2	Net 42
U1:XTAL_24M_I	None	U1:SEN_D3	Net 43
U1:XTAL_24M_O	None	U1:SEN_D1	Net 15
U1:XTAL_24M_O	None	U1:TX_DP1	Net 19
U1:XTAL_24M_O	None	U1:RX_DN1	Net 24
U1:XTAL_24M_O	None	U1:RX_CKN	Net 26
U1:XTAL_24M_O	None	U1:QSPI_DIO0	Net 28
U1:XTAL_24M_O	None	U1:SEN_I2CM_SCL	Net 34
U1:XTAL_24M_O	None	U1:SEN_I2CM_SDA	Net 35
U1:XTAL_24M_O	None	U1:SEN_PCLK	Net 38
U1:XTAL_24M_O	None	U1:SEN_D0	Net 41
U1:XTAL_24M_O	None	U1:SEN_D2	Net 42

Invalid Layer

Reports nodes that are assigned to a layer that doesn't exist in the layout stackup.

Component Overrides

Reports components that have been modified using the "!important" flag.

Airwires • 10

	Designators	Net
	J1:VBUS, J1:VBUS	Net 1
	R2:P1, J1:CC1	Net 2
	R3:P1, J1:CC2	Net 3
	J1:D+, J1:D+	Net 5
	J1:D-, J1:D-	Net 6
	J2:CD/DAT3, D8:K	Net 9
	J2:CMD, D7:K	Net 10
	D6:K, J2:CLX	Net 12
	D5 :K, J2:DAT0	Net 13
	U1:SEN_D1, J2:CD	Net 15

Deprecated Rules

Reports nodes that are using rules that are not supported anymore.

Layers with Multiple Fills

Reports layers that have multiple copper fills of different nets. Make sure the Connected Layers rule value of nets with fills is valid.

Floating Copper

Detect any via, trace or copper fill island that is not connected to any net.

Protected Intrusions

Reports intrusions from objects of other nets into polygons or fills that have the Protected layout rule applied.

Manufacturing

Manufacturer Part Number • 1

	Designator	MPN
	J1	None

Parts Available

Beta

Checks that all parts have a part number and are available from distributors.

System Checks

Auto-Layout

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Reports issues with Auto-Layout if Flux cannot route something or must ignore a configuration.

Passive Components

Resistor Power Rating

Beta

Checks that the power traveling across a given resistor is under its rating with 50% headroom.

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Pull Up/Pull Down Presence

Beta

Checks that IC pins that require pull up or pull down resistors have them.

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Capacitor Voltage Rating

Beta

Checks that capacitors have appropriate voltage ratings to prevent overheating and ensure reliable circuit operation.

Ground
A common return path for electric current. Commonly known as ground.
jharwinbarrozo
20.5M
Net Portal
Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
jharwinbarrozo
43.0M
Power Net Portal
Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power
jharwinbarrozo
11.4M
Generic Resistor
A generic fixed resistor for rapid developing circuit topology. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard resistor values: 1.0Ω 10Ω 100Ω 1.0kΩ 10kΩ 100kΩ 1.0MΩ 1.1Ω 11Ω 110Ω 1.1kΩ 11kΩ 110kΩ 1.1MΩ 1.2Ω 12Ω 120Ω 1.2kΩ 12kΩ 120kΩ 1.2MΩ 1.3Ω 13Ω 130Ω 1.3kΩ 13kΩ 130kΩ 1.3MΩ 1.5Ω 15Ω 150Ω 1.5kΩ 15kΩ 150kΩ 1.5MΩ 1.6Ω 16Ω 160Ω 1.6kΩ 16kΩ 160kΩ 1.6MΩ 1.8Ω 18Ω 180Ω 1.8KΩ 18kΩ 180kΩ 1.8MΩ 2.0Ω 20Ω 200Ω 2.0kΩ 20kΩ 200kΩ 2.0MΩ 2.2Ω 22Ω 220Ω 2.2kΩ 22kΩ 220kΩ 2.2MΩ 2.4Ω 24Ω 240Ω 2.4kΩ 24kΩ 240kΩ 2.4MΩ 2.7Ω 27Ω 270Ω 2.7kΩ 27kΩ 270kΩ 2.7MΩ 3.0Ω 30Ω 300Ω 3.0KΩ 30KΩ 300KΩ 3.0MΩ 3.3Ω 33Ω 330Ω 3.3kΩ 33kΩ 330kΩ 3.3MΩ 3.6Ω 36Ω 360Ω 3.6kΩ 36kΩ 360kΩ 3.6MΩ 3.9Ω 39Ω 390Ω 3.9kΩ 39kΩ 390kΩ 3.9MΩ 4.3Ω 43Ω 430Ω 4.3kΩ 43KΩ 430KΩ 4.3MΩ 4.7Ω 47Ω 470Ω 4.7kΩ 47kΩ 470kΩ 4.7MΩ 5.1Ω 51Ω 510Ω 5.1kΩ 51kΩ 510kΩ 5.1MΩ 5.6Ω 56Ω 560Ω 5.6kΩ 56kΩ 560kΩ 5.6MΩ 6.2Ω 62Ω 620Ω 6.2kΩ 62KΩ 620KΩ 6.2MΩ 6.8Ω 68Ω 680Ω 6.8kΩ 68kΩ 680kΩ 6.8MΩ 7.5Ω 75Ω 750Ω 7.5kΩ 75kΩ 750kΩ 7.5MΩ 8.2Ω 82Ω 820Ω 8.2kΩ 82kΩ 820kΩ 8.2MΩ 9.1Ω 91Ω 910Ω 9.1kΩ 91kΩ 910kΩ 9.1MΩ #generics #CommonPartsLibrary
jharwinbarrozo
1.5M
Generic Capacitor
A generic fixed capacitor ideal for rapid circuit topology development. You can choose between polarized and non-polarized types, its symbol and the footprint will automatically adapt based on your selection. Supported options include standard SMD sizes for ceramic capacitors (e.g., 0402, 0603, 0805), SMD sizes for aluminum electrolytic capacitors, and through-hole footprints for polarized capacitors. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard capacitor values: 1.0pF 10pF 100pF 1000pF 0.01uF 0.1uF 1.0uF 10uF 100uF 1000uF 10,000uF 1.1pF 11pF 110pF 1100pF 1.2pF 12pF 120pF 1200pF 1.3pF 13pF 130pF 1300pF 1.5pF 15pF 150pF 1500pF 0.015uF 0.15uF 1.5uF 15uF 150uF 1500uF 1.6pF 16pF 160pF 1600pF 1.8pF 18pF 180pF 1800pF 2.0pF 20pF 200pF 2000pF 2.2pF 22pF 20pF 2200pF 0.022uF 0.22uF 2.2uF 22uF 220uF 2200uF 2.4pF 24pF 240pF 2400pF 2.7pF 27pF 270pF 2700pF 3.0pF 30pF 300pF 3000pF 3.3pF 33pF 330pF 3300pF 0.033uF 0.33uF 3.3uF 33uF 330uF 3300uF 3.6pF 36pF 360pF 3600pF 3.9pF 39pF 390pF 3900pF 4.3pF 43pF 430pF 4300pF 4.7pF 47pF 470pF 4700pF 0.047uF 0.47uF 4.7uF 47uF 470uF 4700uF 5.1pF 51pF 510pF 5100pF 5.6pF 56pF 560pF 5600pF 6.2pF 62pF 620pF 6200pF 6.8pF 68pF 680pF 6800pF 0.068uF 0.68uF 6.8uF 68uF 680uF 6800uF 7.5pF 75pF 750pF 7500pF 8.2pF 82pF 820pF 8200pF 9.1pF 91pF 910pF 9100pF #generics #CommonPartsLibrary
jharwinbarrozo
1.5M
Generic Inductor
A generic fixed inductor for rapid developing circuit topology. *You can now change the footprint and 3D model at the top level anytime you want. This is the power of #generics
jharwinbarrozo
15.1k
Terminal
An electrical connector acting as reusable interface to a conductor and creating a point where external circuits can be connected.
natarius
RMCF0805JT47K0
47 kOhms ±5% 0.125W, 1/8W Chip Resistor 0805 (2012 Metric) Automotive AEC-Q200 Thick Film #forLedBlink
jharwinbarrozo
1.2M
875105359001
10uF Capacitor Aluminum Polymer 20% 16V SMD 5x5.3mm #forLedBlink #commonpartslibrary #capacitor #aluminumpolymer #radialcan
jharwinbarrozo
1.2M
CTL1206FYW1T
Yellow 595nm LED Indication - Discrete 1.7V 1206 (3216 Metric) #forLedBlink
jharwinbarrozo
1.1M

Inspect

Grove Vision AI schematic

Controls

Properties

Availability & Pricing

Distributor		Qty 1
	Digi-Key	$0.20–$1.32
	LCSC	$0.12–$0.18
	Mouser	$1.28

Assets

Footprint

WLCSP65_5.6x2.3x0.56mm.kicad_mod

id=WLCSP65_5.6x2.3x0.56mm

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