I’ll inspect the remaining GND-related unrouted connections, then try to replace pad-to-pad GND airwires with short pad-to-via drops into the Mid-Layer 2 GND plane where feasible, and verify airwires afterward.
I found the GND-related airwires: they are from existing GND stitch vias to C10:P2 and U1:GND. I’m going to try routing those two short connections directly to the nearby stitch vias rather than doing broad re-routing.
I hit a schematic-net artifact while verifying the GND airwires, so I’m rolling back only the subsequent failed RUN-net repair attempts to avoid leaving RUN tied to GND. The GND via/tie work completed before those attempts will be preserved.
I added two GND drop connections into the Mid-Layer 2 plane path: one near C10:P2 and one near U1 exposed GND, reducing airwire count from 29 → 27.
Open items:
While verifying, a schematic net artifact caused RUN/reset pins to appear tied to GND; I attempted rollback, but the history revert failed with a platform PersistError.
I escalated this internally. Please avoid manufacturing/export until the RUN vs GND net state is reviewed/restored.