AI Availability Inquiry
Worked
I found the GND-related airwires: they are from existing GND stitch vias to C10:P2 and U1:GND. I’m going to try routing those two short connections directly to the nearby stitch vias rather than doing broad re-routing.
Worked
I hit a schematic-net artifact while verifying the GND airwires, so I’m rolling back only the subsequent failed RUN-net repair attempts to avoid leaving RUN tied to GND. The GND via/tie work completed before those attempts will be preserved.
Worked
I added two GND drop connections into the Mid-Layer 2 plane path: one near C10:P2 and one near U1 exposed GND, reducing airwire count from 29 → 27.
Open items:
- While verifying, a schematic net artifact caused RUN/reset pins to appear tied to GND; I attempted rollback, but the history revert failed with a platform
PersistError. - I escalated this internally. Please avoid manufacturing/export until the RUN vs GND net state is reviewed/restored.
Suggested next steps:
- Restore to the commit before my RUN-net repair attempts, or contact Flux support: https://docs.flux.ai/Introduction/getting-support
- Re-check
SW_RESET,U1:RUN,R_RUN:P1,C_RUN:P1, andJ7:6. - Re-run ERC/airwires after restoration.
Restore and verify
Fix RUN net
Inspect bad commits
Run ERC airwires
Remove added vias
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Board Bring-Up Plan — RP2350 Dual-Port SAS USB Interface
Prerequisites
- Equipment: current-limited USB-C 5V source, multimeter, oscilloscope/logic analyzer, SWD debugger, SAS test fixture or loopback cable.
- Initial current limit: 300mA from USB during first power-up.
- Do not connect casino/EGM field wiring until +3V3, +5V, VCC10, USB enumeration, and GPIO idle states are verified.
1. Visual Inspection
- Check RP2350A QFN orientation and solder bridges.
- Verify USB-C connector tabs and shield soldering.
- Verify Schottky diode orientations for D1/D2/D3 and D_BOOST.
- Verify optocoupler and MAX3232 populate-option policy per port.
2. Power Rail Verification
Table
| Rail | Source | Expected | Measure At | Pass Criteria |
|---|---|---|---|---|
| +5V | USB VBUS | 5.0V | TP2 | 4.75–5.25V |
| +3V3 | AP2112K-3.3 | 3.3V | TP1 | 3.23–3.37V |
| VCC10 | Cable VCC or boost OR | ~9–10V | TP3 | 8.5–10.5V bench mode, cable VCC dominates when present |
| BOOST_SW | TPS61040 switch node | switching waveform | TP4 | No DC short; expected switching when boost active |
| GND | common return | 0V | TP5 | Continuity to USB and port pin 1 |
3. Critical Signal Verification
Table
| Signal | Net | Expected |
|---|---|---|
| RP2350 RUN | RUN | Pulled high to +3V3; button pulls low |
| Crystal | XIN/XOUT | 12MHz oscillation after boot |
| USB | USB_DP/USB_DM | Enumerates as RP2350 USB device |
| QSPI | QSPI_CS/SCK/SD0-3 | Flash activity during boot |
4. Connector and Interface Tests
- J1/J2 pinout: 1 GND, 2 RX board-listens, 3 TX board-transmits, 4 cable VCC.
- Verify cable VCC dividers produce about 2.33V at ADC input for 10V cable VCC.
- Verify cable-live LEDs light from cable VCC without USB power.
- Verify source-mode jumpers J_SRC_A/J_SRC_B are DNP by default.
5. Programming and Debug
- Connect SWD to J7: SWDIO, SWCLK, RUN/reset, +3V3 sense, and GND.
- Confirm target detect, flash test firmware, then verify USB enumeration.
6. Functional Validation
Table
| Test | Expected Result |
|---|---|
| Heartbeat GPIO25 | 1Hz blink on LED_HB |
| Port A TX/RX PIO | 9-bit SAS waveform on logic analyzer header J6 |
| Port B TX/RX PIO | Independent 9-bit SAS waveform on J6 |
| Mode straps | Open = host default; grounded = EGM default |
| Monitor mode indication | Both HOST and EGM LEDs lit |
Open Items
- ERC currently reports unresolved floating pins from support passives, unused MAX3232 channels, headers, and incomplete indicator/charge-pump wiring; resolve before fabrication.
- Confirm exact Phoenix terminal block MPN or approve the 4-position 3.5mm TE-compatible substitute footprint.
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Connector and Interface Tests
5. Programming and Debug
6. Functional Validation
Open Items
