Cortex v0 Schematic Design

Thought for 1 min 13 sec

I’ve made a plan, and started work on it.

Started implementing a plan

#Goal

- Hand-route the 6 remaining unrouted airwires and clean up floating copper on Cortex v0 BLE Audio Wearable, ensuring the preservation of U1 Raytac (RF keepout), PZ1 bottom-center placement, and the six U3 EPAD overlap exceptions.

#Implementation plan

1. Route the specific airwires:

1. Hand-route U1 P0.27 haptic motor enable to Q1 gate on the top layer using standard signal width.

2. Route the PZ1 piezo signal from terminal P2 on the bottom side through C11 to the non-inverting input of U5 MCP6001 with a short, isolated trace away from high-dV/dt nets (LED data, QSPI clock, USB, etc.).

3. Identify the GND_3 airwire and connect it to the nearest available ground via.

2. Clean up copper and resolve fill/stitching issues:

1. Regenerate the inner ground plane copper pour to resolve the three c37d412e fill/stitching items and add stitching vias as needed.

2. Delete the floating copper fragments: Trace 1692, 5ef0, 60f6, 7849, c80a, and e493.

3. Final verification:

1. Rerun airwire and DRC checks.

2. Confirm that only the six documented U3 EPAD overlap exceptions remain.

#Success criteria

- U1 P0.27 is routed to Q1 gate on top layer with correct trace width.

- PZ1 piezo signal correctly routed through C11 to U5 MCP6001 non-inverting input with required isolation.

- GND_3 is connected to ground via.

- Ground plane copper pour is updated, fill/stitching issues resolved, and all specified floating copper fragments are deleted.

- Post-fix DRC and airwire checks indicate only the accepted U3 EPAD exceptions remain.

Task unable to complete.

1:14

Thought for 4 sec — Considering PCB-Routing Skills

Looking up PCB routing airwire remediation floating copper cl....

Getting a layout overview.

Thought for 3 sec

flux

Status

I re-ran the focused DRC/airwire checks and updated the itemized report in Post-Route DRC and Airwire Report. The current state is unchanged: 6 airwires, 6 floating-copper fragments, and the 6 accepted U3 EPAD overlap exceptions remain.

Blocker

I can’t complete the requested hand-routing or delete the specified orphan trace fragments from here because the available layout actions do not expose direct trace/via routing or trace-fragment deletion for those PCB UIDs. Manual PCB editor intervention is needed for P0.27, P2, GND_3, the c37d412e fill/stitching items, and floating traces 1692, 5ef0, 60f6, 7849, c80a, and e493.

Next steps

Hand-fix the listed traces/fragments in the PCB editor, then I can re-run DRC/airwire validation and confirm that only the six documented U3 EPAD exceptions remain.

Rerun validation

Locate fragments

Regenerate copper pour

List airwire endpoints

Refine this doc

Ask about this doc

Disconnected Pin Audit — Cortex v0

Generated after reviewing the live schematic connectivity and the latest ERC floating-pin review.

Bottom line

The disconnected pins reported during rewiring were mostly temporary disconnects used to move nets from the first-pass wiring to the revised architecture. In the current schematic, all power/regulator, QSPI, I2S, LED power, and SWD pins affected by those disconnect operations are reconnected correctly, except for intentionally unused spare MCU GPIOs and the WS2812B DOUT pin.

The current ERC floating-pin review reports 6 floating pins:

U1:P0.19
U1:P0.20
U1:P0.21
U1:P0.22
U1:P0.23
LED1:DOUT

These are not power pins. They should either receive explicit No Connect markers if intentionally unused, or be assigned to a future function/test pad if desired.

Batch 1 disconnects — power-path rewiring

These were disconnected while moving the system input rail from unswitched VBAT to switched VBAT_SW, and while moving the WS2812B supply from direct 3V3 to a load-switched rail.

Table

Reported disconnected pin	Current status	Intentional?	Action needed
`LED1:VDD`	Reconnected to `WS2812_VDD_SW` via `U6:VOUT` / `U6:QOD`	Yes — intentionally moved off direct `3V3`	No electrical fix needed. This implements LED rail power gating.
`U3:VIN::10`	Reconnected to `VBAT_SW`	Yes	No fix needed.
`U3:VIN::11`	Reconnected to `VBAT_SW`	Yes	No fix needed.
`U3:VINA`	Reconnected to `VBAT_SW`	Yes	No fix needed.
`U3:EN`	Reconnected to `VBAT_SW`	Yes	No fix needed. If firmware-controlled regulator enable is later desired, route this to an MCU/supervisor instead.
`U3:PS/SYNC`	Reconnected to `VBAT_SW`	Yes	No fix needed. This ties the mode/sync control high with the switched battery rail.
`R6:P1`	`R6` was removed	Yes	No fix needed. Removed because the piezo-to-ADC path was replaced by the MCP6001 buffer/filter.
`R6:P2`	`R6` was removed	Yes	No fix needed. Removed because the piezo-to-ADC path was replaced by the MCP6001 buffer/filter.

Note: the tool output counted repeated U3:VIN entries because the TPS63020 has duplicate VIN pins; both VIN pins are now on VBAT_SW.

Batch 2 disconnects — QSPI/I2S pin reassignment

These were disconnected while moving QSPI onto the requested P0.13–P0.18 range and moving I2S onto P1.00–P1.02.

Table

Reported disconnected pin	Current status	Intentional?	Action needed
`U1:P0.13`	Reconnected to `QSPI_SCK`	Yes	No fix needed.
`U1:P0.14`	Reconnected to `QSPI_CS_FLASH`	Yes	No fix needed.
`U1:P0.15`	Reconnected to `QSPI_IO0`	Yes	No fix needed.
`U1:P0.16`	Connected to `QSPI_IO1`	Yes	No fix needed. This pin was part of the final QSPI assignment.
`U1:P0.17`	Reconnected to `QSPI_IO2`	Yes	No fix needed.
`U1:P0.18`	Connected to `QSPI_IO3`	Yes	No fix needed. This pin was part of the final QSPI assignment.
`U1:P0.19`	Currently floating; ERC warning	Yes, if treated as spare GPIO	Add No Connect marker or reserve as optional test/GPIO. Do not tie directly to GND unless firmware/boot requirements say so.
`U1:P0.20`	Currently floating; ERC warning	Yes, if treated as spare GPIO	Add No Connect marker or reserve as optional test/GPIO. No pull required unless assigned later.
`U1:P0.21`	Currently floating; ERC warning	Yes, if treated as spare GPIO	Add No Connect marker or reserve as optional test/GPIO. No pull required unless assigned later.
`U1:P0.22`	Currently floating; ERC warning	Yes, if treated as spare GPIO	Add No Connect marker or reserve as optional test/GPIO. No pull required unless assigned later.
`U1:P0.23`	Currently floating; ERC warning	Yes, if treated as spare GPIO	Add No Connect marker or reserve as optional test/GPIO. No pull required unless assigned later.
`U4:~CS`	Reconnected to `QSPI_CS_FLASH`	Yes	No fix needed.
`U4:CLK`	Reconnected to `QSPI_SCK`	Yes	No fix needed.
`U4:DI(IO0)`	Reconnected to `QSPI_IO0`	Yes	No fix needed.
`U4:DO(IO1)`	Reconnected to `QSPI_IO1`	Yes	No fix needed.
`U4:IO2`	Reconnected to `QSPI_IO2`	Yes	No fix needed.
`U4:IO3`	Reconnected to `QSPI_IO3`	Yes	No fix needed.
`MK1:BCLK`	Reconnected to `I2S_BCLK` on `U1:P1.00`	Yes	No fix needed.
`MK1:WS`	Reconnected to `I2S_LRCLK` on `U1:P1.01`	Yes	No fix needed.
`MK1:DATA_OUT`	Reconnected to `I2S_SD` on `U1:P1.02`	Yes	No fix needed.

Other floating pin found by ERC

Table

Pin	Current status	Intentional?	Action needed
`LED1:DOUT`	Floating; ERC warning	Yes, because there is only one WS2812B in the chain	Add a No Connect marker. Do not tie to GND or pull up/down.

Substitution / one-for-one replacement notes

SWD header substitution

The main one-for-one substitution was J3:

Original J3: Conn_02x03-TSM-103-01-L-DV, a 2×3 SWD-style header.
New J3: TSW-105-07-G-S, a 1×5 2.54 mm header.

Reason: the updated requirement asked for a 5-pin SWD interface: VDD, SWDIO, GND, SWDCLK, and RESET. A TC2030 footprint would be preferable if available, but the available fallback was the 2.54 mm 5-pin header.

Symbol refreshes that looked like substitutions

I also used an add/remove pattern on U4 and MK1 to clear stale net membership after the QSPI/I2S reassignment:

U4 remained W25Q128JVSIQ; this was not an MPN change.
MK1 remained SPH0645LM4H-B; this was not an MPN change.

The reason was net hygiene: after disconnecting/reassigning the QSPI and I2S nets, refreshing those components made it easier to ensure QSPI_IO0 and I2S_SD were separated correctly and then reconnected cleanly.

Recommended cleanup

Add explicit No Connect markers to:

U1:P0.19
U1:P0.20
U1:P0.21
U1:P0.22
U1:P0.23
LED1:DOUT

No pins from the disconnect batches need to be tied to ground or pulled up/down based on the current schematic. The remaining floating items are spare MCU GPIOs plus the unused WS2812B chain output.

Bottom line
Batch 1 disconnects — power-path rewiring
Batch 2 disconnects — QSPI/I2S pin reassignment
Other floating pin found by ERC
Substitution / one-for-one replacement notes
SWD header substitution
Symbol refreshes that looked like substitutions
Recommended cleanup

Reviews

Documents

Cortex v0 Project Specification

Cortex v0 Design Notes

Disconnected Pin Audit — Cortex v0

32 mm Layout Feasibility — Cortex v0

U3 TPS63020 Footprint Verification

Post-Route DRC and Airwire Report

Assets

No assets added.

Project Name

Cortex v0 BLE Audio Wearable

Description

Cortex v0 tiny AI wearable schematic: Raytac MDBT53V-1M BLE/nRF5340 module, USB-C LiPo charging, TPS63020 3.3V buck-boost, dual microphones, QSPI flash, tactile button, and WS2812B LED on a ~30mm round 4-layer PCB.

Properties

Accepted…ception

U3 TPS63020 EPAD: six overlapping-copper DRC errors accepted for v0 with note accepted-with-known-limitation: thermal vias missing, fix in rev-A.

Pricing & Availability

Distributor	Qty 1
Arrow	$4.69–$6.81
Digi-Key	$7.01–$10.65
HQonline	$5.70
LCSC	$19.06–$20.41
Mouser	$8.35
TME	$2.50
Verical	$4.19–$37.71

Controls

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checht / Cortex v0 BLE Audio Wearable

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