Cortex v0 Schematic Design

C

checht

Hand-route the 6 remaining unrouted airwires and clean up floating copper. Specifically:
  1. P0.27 (haptic motor enable): route a trace from U1 (Raytac) pin P0.27 to Q1 (2N7002) gate. Standard signal width, preferred top layer.
  2. P2 (piezo signal): route from PZ1 terminal P2 on bottom side to MCP6001 (U5) non-inverting input via the C11 coupling cap. Keep this on the bottom side near PZ1, minimize trace length, no nearby high-dV/dt nets.
  3. GND_3: identify which component pin needs grounding and route to nearest ground via.
  4. The three c37d412e fill/stitching items: regenerate the ground copper pour on inner ground plane and add stitching vias as needed to resolve.
  5. Delete the 6 floating copper trace fragments (Trace 1692, 5ef0, 60f6, 7849, c80a, e493) — they’re orphaned and serve no purpose. After all five fixes, re-run airwire and DRC checks. Report final counts. The only acceptable remaining errors are the 6 documented U3 EPAD exceptions

flux

I’ve made a plan, and started work on it.

Started implementing a plan

#Goal

- Hand-route the 6 remaining unrouted airwires and clean up floating copper on Cortex v0 BLE Audio Wearable, ensuring the preservation of U1 Raytac (RF keepout), PZ1 bottom-center placement, and the six U3 EPAD overlap exceptions.

#Implementation plan

1. Route the specific airwires:

1. Hand-route U1 P0.27 haptic motor enable to Q1 gate on the top layer using standard signal width.

2. Route the PZ1 piezo signal from terminal P2 on the bottom side through C11 to the non-inverting input of U5 MCP6001 with a short, isolated trace away from high-dV/dt nets (LED data, QSPI clock, USB, etc.).

3. Identify the GND_3 airwire and connect it to the nearest available ground via.

2. Clean up copper and resolve fill/stitching issues:

1. Regenerate the inner ground plane copper pour to resolve the three c37d412e fill/stitching items and add stitching vias as needed.

2. Delete the floating copper fragments: Trace 1692, 5ef0, 60f6, 7849, c80a, and e493.

3. Final verification:

1. Rerun airwire and DRC checks.

2. Confirm that only the six documented U3 EPAD overlap exceptions remain.

#Success criteria

- U1 P0.27 is routed to Q1 gate on top layer with correct trace width.

- PZ1 piezo signal correctly routed through C11 to U5 MCP6001 non-inverting input with required isolation.

- GND_3 is connected to ground via.

- Ground plane copper pour is updated, fill/stitching issues resolved, and all specified floating copper fragments are deleted.

- Post-fix DRC and airwire checks indicate only the accepted U3 EPAD exceptions remain.

Task unable to complete.

1:14

Thought for 4 sec — Considering PCB-Routing Skills
Looking up PCB routing airwire remediation floating copper cl....
Getting a layout overview.

flux

Status
I re-ran the focused DRC/airwire checks and updated the itemized report in Post-Route DRC and Airwire Report. The current state is unchanged: 6 airwires, 6 floating-copper fragments, and the 6 accepted U3 EPAD overlap exceptions remain.
Blocker
I can’t complete the requested hand-routing or delete the specified orphan trace fragments from here because the available layout actions do not expose direct trace/via routing or trace-fragment deletion for those PCB UIDs. Manual PCB editor intervention is needed for P0.27, P2, GND_3, the c37d412e fill/stitching items, and floating traces 1692, 5ef0, 60f6, 7849, c80a, and e493.
Next steps
Hand-fix the listed traces/fragments in the PCB editor, then I can re-run DRC/airwire validation and confirm that only the six documented U3 EPAD exceptions remain.
Rerun validation
Locate fragments
Regenerate copper pour
List airwire endpoints
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Files

Schematic

Layout

Preview

U3 TPS63020 Footprint Verification
Requirement
Update U3 (TPS63020DSJR) to a corrected TI DSJ/VSON-14 footprint:
  • Body: 3 mm × 4 mm
  • Pin pitch: 0.5 mm
  • Exposed thermal pad: 1.58 mm × 2.85 mm, tied to PGND/GND
  • Thermal vias: 2 × 4 array, 0.3 mm drilled vias inside EPAD
  • Vias must have proper top and bottom copper pads connected to the inner ground plane
  • Focused U3 DRC must report zero copper overlaps before routing
Datasheet extraction result
From the U3 TPS63020 datasheet:
  • Device package is 14-pin VSON DSJ measuring 3 mm × 4 mm.
  • The package has an exposed thermal pad.
  • The exposed thermal pad is connected to PGND.
  • Pin pitch requirement is 0.5 mm per DSJ/VSON-14 land pattern requirement in the execution brief.
Current U3 footprint inspection
Current U3 layout footprint has:
  • EPAD pad size: 1.58 mm × 2.85 mm on GND.
  • Six internal circular mount pads named V inside EPAD.
  • Each current internal circular pad is 0.508 mm diameter.
  • Current internal via pattern is 2 × 3, not 2 × 4.
  • Current internal pads are represented as top-layer copper pads overlapping EPAD, which causes overlap DRC.
Gap against requirement
The current footprint does not satisfy the required corrected geometry because:
  • It has six internal pads, not eight.
  • It uses 0.508 mm circular copper pads rather than 0.3 mm drilled vias with proper top/bottom copper pads.
  • The current via/mount primitives are modeled as overlapping copper inside the EPAD, producing DRC overlap violations.
Implementation blocker
The available project-edit tools can inspect layout nodes and change layout rules, but they cannot create or replace a custom part footprint geometry for U3, nor add two additional thermal via padstack primitives inside the existing footprint asset and connect them as through-vias to the inner GND plane. The current TPS63020 part asset is fixed.
Required manual/library action
A corrected TPS63020DSJR / DSJ0014A footprint asset must be created or imported into the Flux library/part project with:
  • 14 perimeter pads, 0.5 mm pitch
  • 3 mm × 4 mm body/courtyard
  • 1.58 mm × 2.85 mm EPAD assigned to PGND/GND
  • 2 × 4 thermal via array inside EPAD
  • 0.3 mm drill on each via
  • top and bottom annular copper pads connected to GND and inner ground plane
After that corrected footprint is available, U3 can be replaced/updated and focused DRC should be rerun for design_rule_check_overlapping_copper on U3 before routing.

  • Requirement

  • Datasheet extraction result

  • Current U3 footprint inspection

  • Gap against requirement

  • Implementation blocker

  • Required manual/library action