Cortex v0 Schematic Design

1:13

Thought for 6 sec

Analyzing in depth.

Thought for 25 sec

Thought for 1 sec

I’ve made a plan, and started work on it.

Started implementing a plan

#Goal

- Hand-route the 6 remaining unrouted airwires and clean up floating copper on Cortex v0 BLE Audio Wearable, ensuring the preservation of U1 Raytac (RF keepout), PZ1 bottom-center placement, and the six U3 EPAD overlap exceptions.

#Implementation plan

1. Route the specific airwires:

1. Hand-route U1 P0.27 haptic motor enable to Q1 gate on the top layer using standard signal width.

2. Route the PZ1 piezo signal from terminal P2 on the bottom side through C11 to the non-inverting input of U5 MCP6001 with a short, isolated trace away from high-dV/dt nets (LED data, QSPI clock, USB, etc.).

3. Identify the GND_3 airwire and connect it to the nearest available ground via.

2. Clean up copper and resolve fill/stitching issues:

1. Regenerate the inner ground plane copper pour to resolve the three c37d412e fill/stitching items and add stitching vias as needed.

2. Delete the floating copper fragments: Trace 1692, 5ef0, 60f6, 7849, c80a, and e493.

3. Final verification:

1. Rerun airwire and DRC checks.

2. Confirm that only the six documented U3 EPAD overlap exceptions remain.

#Success criteria

- U1 P0.27 is routed to Q1 gate on top layer with correct trace width.

- PZ1 piezo signal correctly routed through C11 to U5 MCP6001 non-inverting input with required isolation.

- GND_3 is connected to ground via.

- Ground plane copper pour is updated, fill/stitching issues resolved, and all specified floating copper fragments are deleted.

- Post-fix DRC and airwire checks indicate only the accepted U3 EPAD exceptions remain.

Task unable to complete.

1:14

Thought for 4 sec

Read knowledge.

Read layout.

0:03

Status
I re-ran the focused DRC/airwire checks and updated the itemized report in Post-Route DRC and Airwire Report. The current state is unchanged: 6 airwires, 6 floating-copper fragments, and the 6 accepted U3 EPAD overlap exceptions remain.
Blocker
I can’t complete the requested hand-routing or delete the specified orphan trace fragments from here because the available layout actions do not expose direct trace/via routing or trace-fragment deletion for those PCB UIDs. Manual PCB editor intervention is needed for P0.27, P2, GND_3, the c37d412e fill/stitching items, and floating traces 1692, 5ef0, 60f6, 7849, c80a, and e493.
Next steps
Hand-fix the listed traces/fragments in the PCB editor, then I can re-run DRC/airwire validation and confirm that only the six documented U3 EPAD exceptions remain.
Rerun validation
Locate fragments
Regenerate copper pour
List airwire endpoints

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Cortex v0 Project Specification
Goal
Tiny AI device that captures audio from two microphones and streams data to a phone over BLE using the Raytac MDBT53V-1M nRF5340 module.
Major Blocks
  • Power: USB-C 5V input, MCP73831 single-cell LiPo charger, 500mAh LiPo connector, TPS63020 buck-boost regulator for 3V3.
  • MCU/BLE: Raytac MDBT53V-1M module with SWD programming/debug access.
  • Audio/Peripherals: Knowles SPH0645LM4H-B I2S digital microphone and Murata 7BB-20-6L0 piezo contact microphone routed to ADC.
  • Memory: W25Q128JV 16MB QSPI flash.
  • UI/Connectors: tactile button and WS2812B status LED.
Schematic Net Naming
  • Power: USB_VBUS, VBAT, 3V3, GND.
  • I2S: I2S_BCLK, I2S_LRCLK, I2S_SD.
  • QSPI: QSPI_SCK, QSPI_CS_FLASH, QSPI_IO0, QSPI_IO1, QSPI_IO2, QSPI_IO3.
  • UI/Analog: PIEZO_ADC, BTN_USER, WS2812_DIN, SWDIO, SWDCLK, RESET_N.
Assumptions
  • All logic/peripheral signals are 3.3V and directly connected unless later datasheet review requires otherwise.
  • GPIO assignments are provisional and documented in design notes for firmware handoff.
  • Board target is 4-layer and approximately 30mm round for the PCB stage.

    Goal

    Major Blocks

    Schematic Net Naming

    Assumptions

Documents

    Cortex v0 Project Specification

    Cortex v0 Design Notes

    Disconnected Pin Audit — Cortex v0

    32 mm Layout Feasibility — Cortex v0

    U3 TPS63020 Footprint Verification

    Post-Route DRC and Airwire Report

Assets

No assets added.

Cortex v0 BLE Audio Wearable

Cortex v0 BLE Audio Wearable thumbnail
Cortex v0 tiny AI wearable schematic: Raytac MDBT53V-1M BLE/nRF5340 module, USB-C LiPo charging, TPS63020 3.3V buck-boost, dual microphones, QSPI flash, tactile button, and WS2812B LED on a ~30mm round 4-layer PCB.

Properties

U3 TPS63020 EPAD: six overlapping-copper DRC errors accepted for v0 with note accepted-with-known-limitation: thermal vias missing, fix in rev-A.

Pricing & Availability

Distributor

Qty 1

Arrow

$4.69–$6.81

Digi-Key

$7.01–$10.65

HQonline

$5.70

LCSC

$19.06–$20.41

Mouser

$8.35

TME

$2.50

Verical

$4.19–$37.71

Controls