Cortex v0 Schematic Design
Started implementing a plan
#Goal
- Hand-route the 6 remaining unrouted airwires and clean up floating copper on Cortex v0 BLE Audio Wearable, ensuring the preservation of U1 Raytac (RF keepout), PZ1 bottom-center placement, and the six U3 EPAD overlap exceptions.
#Implementation plan
1. Route the specific airwires:
1. Hand-route U1 P0.27 haptic motor enable to Q1 gate on the top layer using standard signal width.
2. Route the PZ1 piezo signal from terminal P2 on the bottom side through C11 to the non-inverting input of U5 MCP6001 with a short, isolated trace away from high-dV/dt nets (LED data, QSPI clock, USB, etc.).
3. Identify the GND_3 airwire and connect it to the nearest available ground via.
2. Clean up copper and resolve fill/stitching issues:
1. Regenerate the inner ground plane copper pour to resolve the three c37d412e fill/stitching items and add stitching vias as needed.
2. Delete the floating copper fragments: Trace 1692, 5ef0, 60f6, 7849, c80a, and e493.
3. Final verification:
1. Rerun airwire and DRC checks.
2. Confirm that only the six documented U3 EPAD overlap exceptions remain.
#Success criteria
- U1 P0.27 is routed to Q1 gate on top layer with correct trace width.
- PZ1 piezo signal correctly routed through C11 to U5 MCP6001 non-inverting input with required isolation.
- GND_3 is connected to ground via.
- Ground plane copper pour is updated, fill/stitching issues resolved, and all specified floating copper fragments are deleted.
- Post-fix DRC and airwire checks indicate only the accepted U3 EPAD exceptions remain.
Task unable to complete.
1:14
P0.27, P2, GND_3, the c37d412e fill/stitching items, and floating traces 1692, 5ef0, 60f6, 7849, c80a, and e493.- QSPI flash W25Q128JV:
- P0.13: QSPI_SCK
- P0.14: QSPI_CS_FLASH
- P0.15: QSPI_IO0
- P0.16: QSPI_IO1
- P0.17: QSPI_IO2
- P0.18: QSPI_IO3
- I2S microphone SPH0645LM4H-B:
- P1.00: I2S_BCLK
- P1.01: I2S_LRCLK / WS
- P1.02: I2S_SD from DATA_OUT
- SELECT tied to GND.
- Piezo contact microphone ADC:
- MCP6001 unity-gain buffer on 3V3.
- Piezo bias/input node: PIEZO_BIAS.
- Piezo bias divider: R7 = 10MΩ from 3V3 to PIEZO_BIAS and R8 = 10MΩ from PIEZO_BIAS to GND, creating ~1.65V mid-rail bias with ~5MΩ Thevenin source impedance. This follows the user requirement for very high impedance biasing of the capacitive piezo source.
- Buffered output: PIEZO_BUF_OUT.
- Anti-alias filter: R11 = 40kΩ series and C17 = 1nF shunt, approximately 4 kHz cutoff, feeding P0.28 / PIEZO_ADC.
- Battery monitor:
- P0.29: VBAT_SENSE.
- Divider: R12 = 1MΩ from VBAT to VBAT_SENSE, R13 = 1MΩ from VBAT_SENSE to GND, C19 = 100nF to GND.
- UI / haptics:
- P0.24: WS2812 data through R10.
- P0.25: Active-low user button.
- P0.26: LED_PWR_EN for TPS22918 WS2812B power load switch.
- P0.27: HAPTIC_MOTOR_EN for Q1 2N7002 coin motor low-side switch.
- Debug:
- J3 is a 5-pin SWD header: 01=3V3, 02=SWDIO, 03=GND, 04=SWDCLK, 05=RESET_N.
- USB-C VBUS is configured as a sink using 5.1kΩ pull-down resistors on CC1 and CC2.
- D1 PESD5V0L1BAZ provides USB_VBUS-to-GND TVS/ESD protection near the USB-C input.
- MCP73831 charges the single-cell LiPo directly from USB_VBUS; its VBAT charger output remains on the unswitched VBAT node.
- SW2 slide switch gates VBAT to VBAT_SW.
- TPS63020 input/control pins VIN, VINA, EN, and PS/SYNC are fed from VBAT_SW, so the 3V3 system rail is off when SW2 is open while charging remains available.
- TPS63020 generates 3V3 from VBAT_SW with existing inductor, input/output capacitors, and feedback network.
- U6 TPS22918 gates WS2812B VDD from 3V3 to WS2812_VDD_SW, controlled by LED_PWR_EN.
- Haptic motor M1 is driven from VBAT_SW through Q1 as a low-side switch; D2 is the flyback diode with cathode to VBAT_SW and anode to MOTOR_LOW.
- U5 MCP6001 has local C18 = 100nF from 3V3 to GND.
- MDBT53/Raytac nRF5340 module has the original regulator/internal-node capacitors plus added bulk/high-frequency bypassing:
- VDD group: C20 100nF, C21 10nF, C22 4.7µF to GND.
- VDDH group: C23 100nF, C24 10nF, C25 4.7µF to GND.
- Piezo ADC path is buffered before the 4 kHz low-pass filter; the former direct passive ADC series resistor was removed.
- PIEZO_BIAS net (5MΩ Thevenin to mid-rail) requires careful layout: short trace, no nearby high-dV/dt nets (LED data, QSPI clock, USB), guard ring tied to PIEZO_BIAS reference voltage preferred, keep solder mask intact in this region.
- Magnets are mechanical BOM items only and are not part of the active schematic.
- Hall sensor / DRV5032 circuitry is intentionally excluded.
- Display peripherals are intentionally excluded.
- The exact Precision Microdrives 310-103 motor was not available in the library; M1 is a generic DC motor placeholder with the intended MPN metadata.
- Current PCB outline is a 35mm × 38mm rounded rectangle with 4mm corner radius.
- Stackup is 4-layer Signal / Ground / Power / Signal.
- Layout constraints: 5 mil minimum trace width and 8 mil minimum drill.
- U1 Raytac MDBT53V-1M is pinned at the board short edge with antenna pointing outward; RF keepout must be preserved on all four copper layers and RF-section routing is excluded from autorouting.
- PZ1 piezo contact mic is pinned on the bottom side at the board geometric center for phone-back contact.
- Component density remains high; routing should preserve current placement and use bottom-side passives where beneficial.
- Accepted v0 exception: the six U3 TPS63020 overlapping-copper DRC errors named EPAD are accepted with note
accepted-with-known-limitation: thermal vias missing, fix in rev-A. - Rationale: these six errors are internal to the U3 footprint EPAD/mount copper region. The TPS63020 EPAD itself is the intended PGND thermal pad, but the current Flux-library footprint cannot be edited in this environment to implement the corrected plated thermal via pattern.
- v0 limitation: U3 thermal performance is accepted for dev-board use based on the user-approved ~0.3W worst-case dissipation and 70°C+ thermal margin to junction max.
- Rev-A action item: replace/correct the U3 TPS63020 DSJ/VSON-14 footprint to include a 2×4 array of 0.3mm drilled plated thermal vias inside the 1.58mm × 2.85mm exposed PGND pad, connected to top/bottom copper and the inner ground plane.
- Pre-route placement status: board is 35mm × 38mm rounded rectangle, U1 remains at the board short edge, and PZ1 remains bottom-centered at (0,0).
- Current airwire status before routing: 97 airwire errors remain, so the board is not routed yet.
- Current accepted DRC exception status: six U3 TPS63020 EPAD overlap errors remain accepted for v0 only.
- Routing constraints to preserve when routing is executed: RF antenna/feedline hand-routing only; keep Raytac RF keepout clear on all copper layers; length-match I2S_BCLK and I2S_LRCLK within 0.5mm; route PIEZO_BIAS short with extra clearance from LED data, QSPI clock, and USB lines.
- Routing could not be completed in this run; final DRC/airwire signoff remains pending.
GPIO / Signal Assignment
Power Architecture
Decoupling / Sensor Front-End
Mechanical / Exclusions
Layout Target
DRC Exceptions / Rev-A Actions
Routing Attempt Status — 2026-05-10
