Raspberry Pi Zero HAT PCB Design

0:06

Work done

Re-audited the live schematic against the remaining plan.
Added the missing eFuse support parts: C7 = 3.3 nF for U1:dVdt and R10 = 100 kΩ for U1:~FLT pull-up.
Confirmed current remaining schematic issues: L2:1 is still floating, J2:P1 is still floating, U1:dVdt/U1:~FLT and new C7/R10 are not yet wired, J6:C still needs explicit NC, TP3 remains a single-pin net, and 41 Net Portals remain.
Updated the handoff mapping with the current blocked state and exact intended repairs: Schematic Text Mapping for Other LLMs.

Success criteria review

✅ Verified existing corrected intent for VIN_6V, BUCK_5V, PI_5V, motors, LED GPIO JSTs, common GND, and feedback values.
✅ Added C7 and R10 parts needed for the eFuse omissions.
❌ Could not safely apply final wiring repairs due to a schematic data issue that is blocking edits.
❌ ERC is not clean yet; remaining warnings include L2:1, J2:P1, U1:dVdt, U1:~FLT, C7, R10, J6:C, TP3, and expected unused Pi header pins.
❌ PCB layout preparation should wait until the schematic edit issue is cleared and the final schematic repairs are verified.

Next steps

Clear the schematic edit issue, then apply the documented repairs: connect L2:1 to U2:SW/C5:P2, connect J2:P1 to MOTOR1_LOW, wire C7 and R10, mark J6:C NC, resolve TP3, remove stale portals, then rerun ERC/DRC before PCB layout setup.

2 days

bubbaa

give a text instructions of exactly what to wire but dont wire yourself.

2 days

flux

1:08

Considering user instructions.

I created a detailed copy-pasteable wiring checklist here: Manual Wiring Instructions - Pi Zero 2 W Power HAT.

It lists the exact pin-to-pin/net wiring for VIN_6V, GND, TPS56339 buck/BOOT/SW/FB, TPS259531 eFuse, motor MOSFET channels, LED JSTs, TP3, and the final ERC checklist.

2 days

bubbaa

I think I wired everything. check my work. do not wire anything yourself but call out what is needed.

2 days

flux

1:25

Considering tool usage for files.

Running design review.

Analyzing the schematic.

Your main functional wiring looks mostly correct now: VIN_6V, buck/eFuse-to-PI_5V, motor low-side switching, LED GPIO connectors, and common GND are all largely in place. Remaining issues are cleanup/ERC hygiene: label the unnamed VIN_6V, BUCK_5V, and GND nets, rename AUTO_NAME to Q2_GATE, mark J6:C NC, resolve/assign TP1–TP4 and 6V:P1, then route the PCB airwires. Full audit is in Schematic Audit — Check My Work.

Run ERC/DRC

List net labels

Check BOM completeness

Inspect airwires

2 days

Refine this doc

Ask about this doc

Schematic Audit — Check My Work

Date: 2026-05-02

Scope: Read-only audit of the current Pi Zero 2 W Power HAT schematic after the user’s manual wiring pass. No project edits were made.

Overall Status

The main topology is close, but the schematic is not yet clean. Key rails and signal paths are mostly present, but there are several items that still need attention before layout:

39 PCB airwire DRC errors remain. These are layout/routing issues, not necessarily schematic connectivity errors.
ERC floating-pin warnings remain for J6:C, several test points, expected-unused Pi header pins, and a 6V:P1 object.
TP3 / Net 22 is still a single-pin net.
Some net names are still unnamed or generic even though the connections appear correct.
Q2_GATE rename did not take; the actual Q2 gate net is still called AUTO_NAME.

What Looks Correct

Barrel Jack and Raw 6 V Rail

Current live netlist shows:

J6:A is on the raw 6 V input rail with U2:VIN, U2:EN, input capacitors, D5:K, D2:K, J1:P2, J2:P2, and C6:1.
J6:B is on the common ground net.

This matches the intended Tensility mapping:

J6:A -> VIN_6V
J6:B -> GND
J6:C -> NC / plug-detect if used

Issue: the raw 6 V rail is currently shown as an unnamed net in the live schematic output, even though the intent is VIN_6V. Rename/label this net back to VIN_6V if it is not visibly labeled in the editor.

Buck Switch Node

The SW node is now present and correctly contains:

U2:SW
C5:P2
L2:1

This addresses the earlier L2:1 floating issue.

Bootstrap Network

Bootstrap wiring appears structurally correct:

BOOT: U2:BOOT, R9:1
BOOT_CAP: R9:2, C5:P1
SW: U2:SW, C5:P2, L2:1

This means the bootstrap path is:

U2:BOOT -> R9 -> C5 -> SW

Buck Output / BUCK_5V

The post-inductor buck output node is present as an unnamed net containing:

L2:2
C3:1
C4:1
F2:1
R6:1

This is the intended BUCK_5V rail. Rename/label this unnamed net to BUCK_5V if it is not visibly labeled.

Ground side of output capacitors:

C3:2 -> GND
C4:2 -> GND

Feedback Divider

Feedback net is correct:

FB: U2:FB, R6:2, R7:P1
R7:P2 -> GND
R6:1 -> BUCK_5V node

Values/properties:

R6 = 76.8 kΩ
R7 = 10 kΩ

This matches the ~5.2 V target from the corrected topology.

eFuse / Pi 5 V Path

The Pi power path appears correct:

BUCK_5V node -> F2:1
F2:2 -> U1_IN
U1_IN: F2:2, U1:IN pins, U1:EN/UVLO
PI_5V: U1:OUT, H1:Pin_2, H1:Pin_4, D1:1, R10:P2

This matches the intended path:

BUCK_5V -> F2 -> TPS259531 eFuse input -> PI_5V -> H1 pins 2 and 4

eFuse dVdt and FLT Support

The newly added support networks now exist:

U1:dVdt connected to C7:P2
C7:P1 -> GND
U1:~FLT connected to R10:P1
R10:P2 -> PI_5V

This resolves the previous real omissions for dVdt and ~FLT.

Motor Low-Side Switches

Motor channel low-side topology is present:

Channel 1:

MOTOR1_LOW: Q1:D, D2:A, J2:P1
D2:K is on raw 6 V rail
Q1:S -> GND
Q1_GATE: Q1:G, R1:2, R3:1
R3:2 -> GND
PWM10: H1:Pin_19, R1:1

Channel 2:

MOTOR2_LOW: Q2:D, D3:A, J1:P1
D3:K is on raw 6 V rail
Q2:S -> GND
Q2 gate net: AUTO_NAME: R2:1, R4:1, Q2:G
R4:2 -> GND
PWM17: H1:Pin_11, R2:2

This is electrically correct. Only the Q2 gate net name needs cleanup.

LED GPIO Connectors

LED connector nets are correct:

GPIO24_LED: H1:Pin_18, J5:Pin_1
GPIO25_LED: H1:Pin_22, J7:Pin_1
J5:Pin_2 -> GND
J7:Pin_2 -> GND

Role notes correctly state these are for LED modules with built-in current limiting; bare LEDs need series resistors or drivers.

Common Ground

The common ground net includes:

J6:B
U2:GND
U1:GND, U1:EP
Q1:S, Q2:S
Pi ground pins including H1:Pin_6, Pin_9, Pin_14, Pin_25, Pin_34, Pin_39
C1:P2, C2:P2, C3:2, C4:2, C6:2
R3:2, R4:2, R7:P2, R_ILM:P2
J5:Pin_2, J7:Pin_2

This matches the single common ground requirement.

What Still Needs Attention

1. Net Names / Labels Need Cleanup

The live schematic still shows these important rails as unnamed nets:

Raw input rail containing J6:A, U2:VIN, U2:EN, D5:K, D2:K, J1:P2, J2:P2, etc. This should be labeled VIN_6V.
Buck output node containing L2:2, C3:1, C4:1, F2:1, R6:1. This should be labeled BUCK_5V.
Main ground net is unnamed in the live output, although it is functionally GND. Make sure it is labeled GND in the editor.

2. Q2 Gate Net Name

Electrical connection is correct, but the net name is still AUTO_NAME:

AUTO_NAME: R2:1, R4:1, Q2:G

Rename this net to Q2_GATE after removing any conflicting duplicate Q2_GATE portal/label.

3. J6:C Floating

ERC reports:

Floating pin: J6:C

If unused, place a No-Connect marker on J6:C. Do not tie it to VIN or GND unless you intentionally use the jack switch/contact behavior.

4. Test Points / Single-Pin Nets

ERC reports floating test points:

TP1:-
TP2:-
TP4:-

Single-pin net warning:

Net 22 has only one pin connected: TP3:-

Action: either connect each test point to the intended rail/signal or mark/remove it. Likely assignments could be:

TP1 -> VIN_6V
TP2 -> BUCK_5V
TP3 -> PI_5V
TP4 -> GND

But verify intended labels/placement before wiring.

5. 6V:P1 Floating

ERC reports:

Floating pin: 6V:P1

This appears to be a leftover power symbol/portal/object. Either connect it to VIN_6V intentionally or remove/NC it if it is a stale artifact.

6. Pi Header Floating Pins

Many unused Pi header pins are floating. That is expected if they are not used, but ERC will continue warning unless you mark unused H1 pins as No-Connect or accept the warnings.

Used H1 pins currently include:

Pin_2, Pin_4: PI_5V
Pin_6, Pin_9, Pin_14, Pin_25, Pin_34, Pin_39: GND
Pin_11: PWM17
Pin_18: GPIO24_LED
Pin_19: PWM10
Pin_22: GPIO25_LED

7. DRC Airwires

DRC reports 39 airwire errors. These are PCB layout routing issues, not necessarily schematic net problems. Once the schematic cleanup items above are handled, the board still needs physical routing or autorouting.

8. Parts Availability

Manufacturer Part Number review passes. Parts Available review is currently unrun, so availability has not been reconfirmed after the latest changes.

Recommended Fix Order

Label unnamed rails:
- raw input rail -> VIN_6V
- buck output node -> BUCK_5V
- common ground -> GND
Rename AUTO_NAME -> Q2_GATE after clearing duplicate label conflict.
Mark J6:C No-Connect.
Resolve test points:
- connect them to intended rails/signals or remove/NC them.
Remove or connect 6V:P1 artifact.
Decide whether to mark unused H1 pins NC or accept warnings.
Re-run ERC.
Run Parts Available review.
Proceed to PCB routing to clear 39 airwires.

Bottom Line

Your main functional wiring looks correct now. The remaining work is mostly cleanup and ERC hygiene: net labels, NC markers, stale artifacts/test points, Q2 gate naming, and then PCB routing.

Overall Status

What Looks Correct

Barrel Jack and Raw 6 V Rail

Buck Switch Node

Bootstrap Network

Buck Output / BUCK_5V

Feedback Divider

eFuse / Pi 5 V Path

eFuse dVdt and FLT Support

Motor Low-Side Switches

LED GPIO Connectors

Common Ground

What Still Needs Attention

1. Net Names / Labels Need Cleanup

2. Q2 Gate Net Name

3. J6:C Floating

4. Test Points / Single-Pin Nets

5. `6V:P1` Floating

6. Pi Header Floating Pins

7. DRC Airwires

8. Parts Availability

Recommended Fix Order

Bottom Line

Reviews

Documents

Schematic Text Mapping for Other LLMs

Manual Wiring Instructions - Pi Zero 2 W Power HAT

Schematic Audit — Check My Work

Assets

No assets added.

Project Name

Stuck Cyan Lightcycle 92e7

Description

Pi Zero 2 W Power HAT – 6 V Input, 5.2 V Buck to Pi 5 V Header via 1.85 A Fuse, Enhanced Input & Pi Rail Protection (TVS + High-Hold PTC + 5 A Schottky)

Properties

Audit Report

Retained: PJ-037A barrel jack; input fuse F1 (RUEF500); Schottky D1 (VS-MBRS340); TVS D2 (SMAJ6.0A); buck converter U1 (TPS56339DDC) with L1 (4.7 µH), C3/C4 (22 µF, CC1206KKX5R6BB226, 1206), C5 (100 nF), divider resistors R_FB_H (75 kΩ) and R_FB_L (10 kΩ); output fuse F2 (RUEF500); USB-A J3; TVS D7 (SP0502BAHT); motor driver Q1/Q2 (AO3400A) with gate resistors R1/R2 (100 Ω), pulldowns R3/R4 (100 kΩ) and flyback diodes D3/D4 (MBR540); RP40 header (PPPC202LFBN-RC 2x20 TH) with test points T10/T17; JST-PH connectors J1/J2. Removed: duplicate net portals; ESD diodes D5 and D6. Net optimizations: consolidated all ground symbols into a single GND net; removed stray portal blocks; validated VIN and 5V_USB rails; ensured PWM10 and PWM17 nets correctly isolated and connected.

Net Type

Power

Prune Report

Net standardization: Confirmed VIN net (VIN) and buck output net (5V_USB) are correctly named and delineated, with Pi 5V remaining isolated from 5V_USB. PWM control nets verified and labeled via RP40 (PPPC202LFBN-RC 2x20 TH): GPIO 10 -> T10 (PWM10) and GPIO 17 -> T17 (PWM17). Pruning: Removed stray/duplicate net portals and non-topology ESD parts; retained only agreed functional blocks (BJ, F1, D1, D2, U1=TPS56339DDC, L1, C1–C5, RFB_H, RFB_L, RBOOT=ERJ-3GEYJ300V, C3/C4=CC1206KKX5R6BB226, F2, D7, J3, Q1/Q2, D3/D4, MT1/MT2, RP40=PPPC202LFBN-RC, J1/J2, T10/T17, mounting holes). Wiring fixes: D4 rewired as flyback between motor node and VIN; EN line implemented with R5 pull-up to 5V_USB and correctly tied to U1:EN; feedback chain and all input/output decoupling capacitors verified against buck topology. Validation: Latest ERC/DRC checks (airwires, missing footprints) are clean with no remaining warnings; parts availability review run for key BOM items with results stored under `Parts Availability Report`. Design is considered pruned, net-standardized, and production-ready for PCB layout and manufacturing.

Parts Av…ed Types

parts_available

Project Description

Pi Zero 2 W Power HAT – Buck Converter Feeds Pi 5V Header via ~1.85 A PTC Fuse (USB Power Output Removed)

Airwire Nets

[]

Net: BUC…et Type

Power

Parts Av…y Report

{"reviewType":"parts_available","results":[{"designator":"C3","available":true,"stock":12500,"distributors":["Digi-Key","Mouser"]},{"designator":"C4","available":true,"stock":13000,"distributors":["Digi-Key","Arrow"]},{"designator":"RBOOT","available":true,"stock":54000,"distributors":["Digikey"]},{"designator":"RP40","available":true,"stock":8500,"distributors":["Mouser"]}]}

Final Ver…n Report

BOOT path modification passed without errors; C3/C4 set to CC1206KKX5R6BB226 (1206), RBOOT set to ERJ-3GEYJ300V (0603), RP40 set to PPPC202LFBN-RC (2x20 TH) with no connectivity changes.

Feedback…t Value

55000

System Architecture

Diagram

ERC/DRC Report

ERC/DRC checks run for: design_rule_check_airwires, design_rule_check_floating_copper. No remaining warnings.

PTC Replacements

F1 (1206L050/15YR): HoldCurrent 0.5 A, Package 1206; F2 (ASMD1206-200): HoldCurrent 1.85 A, Package 1206

Voltage

5.2

Net

BUCK_5V

Net: PiVI…Net Type

Power

Domain

Consumer Electronics

ERC/DRC…d Types

design_rule_check_airwires, design_rule_check_floating_copper

DRC Report

ERC/DRC checks run for: design_rule_check_airwires, design_rule_check_floating_copper. No remaining warnings.

System Architecture

Diagram

Protecti…umented

Input and USB protection paths updated; VIN and PI_5V net names verified; USB-A output and USB_VBUS path removed; buck output now feeds Pi 5V header (H1 pins 2/4) via ~1.85 A PTC fuse F2 with common GND, maintaining ~5.2 V BUCK_5V output.

5V_USB i…nfirmed

Revised: USB-A VBUS path removed; buck output BUCK_5V now routed through ~1.85 A PTC F2 onto PI_5V (H1 pins 2/4). Previous 5V_USB isolation note superseded by new topology.

ERC/DRC…d Types

design_rule_check_airwires, design_rule_check_floating_copper

Manufact…fenders

Buck Out… Voltage

5.2

ERC/DRC Status

Clean

Floating…rIslands

[]

Part Type

Portal

Board Size

65.0 mm x 30.0 mm

Manufact… Target

ERC/DRC Report

ERC/DRC checks run for: design_rule_check_airwires, design_rule_check_floating_copper. No remaining warnings.

Net: VIN …Net Type

Power

Feedback…) Value

10000

License

solderpad.org/licenses/SHL-2.1/

Pricing & Availability

Distributor	Qty 1
Arrow	$2.51–$3.01
Digi-Key	$1.98–$3.39
LCSC	$3.43–$3.79
Mouser	$3.14–$3.44
TME	$1.46
Verical	$1.58–$91.06

Controls

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bubbaa / Stuck Cyan Lightcycle 92e7

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