Raspberry Pi Zero HAT PCB Design

0:06

Work done

Re-audited the live schematic against the remaining plan.
Added the missing eFuse support parts: C7 = 3.3 nF for U1:dVdt and R10 = 100 kΩ for U1:~FLT pull-up.
Confirmed current remaining schematic issues: L2:1 is still floating, J2:P1 is still floating, U1:dVdt/U1:~FLT and new C7/R10 are not yet wired, J6:C still needs explicit NC, TP3 remains a single-pin net, and 41 Net Portals remain.
Updated the handoff mapping with the current blocked state and exact intended repairs: Schematic Text Mapping for Other LLMs.

Success criteria review

✅ Verified existing corrected intent for VIN_6V, BUCK_5V, PI_5V, motors, LED GPIO JSTs, common GND, and feedback values.
✅ Added C7 and R10 parts needed for the eFuse omissions.
❌ Could not safely apply final wiring repairs due to a schematic data issue that is blocking edits.
❌ ERC is not clean yet; remaining warnings include L2:1, J2:P1, U1:dVdt, U1:~FLT, C7, R10, J6:C, TP3, and expected unused Pi header pins.
❌ PCB layout preparation should wait until the schematic edit issue is cleared and the final schematic repairs are verified.

Next steps

Clear the schematic edit issue, then apply the documented repairs: connect L2:1 to U2:SW/C5:P2, connect J2:P1 to MOTOR1_LOW, wire C7 and R10, mark J6:C NC, resolve TP3, remove stale portals, then rerun ERC/DRC before PCB layout setup.

2 days

bubbaa

give a text instructions of exactly what to wire but dont wire yourself.

2 days

flux

1:08

Considering user instructions.

I created a detailed copy-pasteable wiring checklist here: Manual Wiring Instructions - Pi Zero 2 W Power HAT.

It lists the exact pin-to-pin/net wiring for VIN_6V, GND, TPS56339 buck/BOOT/SW/FB, TPS259531 eFuse, motor MOSFET channels, LED JSTs, TP3, and the final ERC checklist.

2 days

bubbaa

I think I wired everything. check my work. do not wire anything yourself but call out what is needed.

2 days

flux

1:25

Considering tool usage for files.

Running design review.

Analyzing the schematic.

Your main functional wiring looks mostly correct now: VIN_6V, buck/eFuse-to-PI_5V, motor low-side switching, LED GPIO connectors, and common GND are all largely in place. Remaining issues are cleanup/ERC hygiene: label the unnamed VIN_6V, BUCK_5V, and GND nets, rename AUTO_NAME to Q2_GATE, mark J6:C NC, resolve/assign TP1–TP4 and 6V:P1, then route the PCB airwires. Full audit is in Schematic Audit — Check My Work.

Run ERC/DRC

List net labels

Check BOM completeness

Inspect airwires

2 days

Refine this doc

Ask about this doc

Manual Wiring Instructions - Pi Zero 2 W Power HAT

Use this as the manual checklist for wiring the schematic. Do not connect by visual proximity alone; connect the exact pins listed here. Net names are shown in CODE_STYLE.

0. Cleanup before wiring

Remove or ignore stale duplicate Net Portal components on power and ground rails.
Use direct pin-to-pin net connections where possible.
Keep exactly these main rails/nets:
- VIN_6V = raw protected/usable 6 V input rail after the barrel jack pin A rail definition.
- GND = single common ground.
- SW = TPS56339 switch node.
- BOOT / BOOT_CAP = bootstrap drive/cap node if R9 is used in series.
- BUCK_5V = TPS56339 regulated output, target about 5.2 V.
- U1_IN = eFuse input after F2.
- PI_5V = eFuse protected output to Raspberry Pi 5 V pins.
- PWM10, Q1_GATE, PWM17, Q2_GATE.
- MOTOR1_LOW, MOTOR2_LOW.
- GPIO24_LED, GPIO25_LED.
Mark J6:C as No Connect unless intentionally used as a plug-detect/switch pin.

1. Barrel jack and raw 6 V rail

Tensility 54-00166 barrel jack mapping:

VIN_6V

Connect these together:

J6:A
U2:VIN
U2:EN
C1:P1
C2:P1
C6:1
D5:K if D5 is the VIN TVS/clamp
J1:P2 motor connector positive
J2:P2 motor connector positive
D2:K flyback diode cathode for motor channel 1
D3:K flyback diode cathode for motor channel 2

GND

Connect these together:

J6:B
U2:GND
C1:P2
C2:P2
C6:2
D5:A if D5 is the VIN TVS/clamp
All Raspberry Pi header ground pins used in the design, including at least H1:Pin_6, H1:Pin_9, H1:Pin_14, H1:Pin_25, H1:Pin_34, H1:Pin_39
Q1:S
Q2:S
R3:2
R4:2
R7:P2
C3:2
C4:2
D1:2 if D1 is the PI_5V TVS/clamp to ground
U1:GND
U1:EP
R_ILM:P2
J5:Pin_2
J7:Pin_2

No connect

J6:C -> No Connect, unless intentionally used for plug detect.

2. TPS56339 buck converter U2

Target output is about 5.2 V using R6 = 76.8 kOhm top and R7 = 10 kOhm bottom.

Buck input

Already covered under VIN_6V:

U2:VIN -> VIN_6V
U2:EN -> VIN_6V for always-on buck behavior
U2:GND -> GND

Switch node SW

Connect exactly these together:

U2:SW
L2:1
C5:P2

This is the current highest-priority missing repair: L2:1 must be on this SW net.

Bootstrap network with R9

Use the series boot resistor arrangement:

U2:BOOT -> R9:1 on net BOOT
R9:2 -> C5:P1 on net BOOT_CAP
C5:P2 -> SW net (U2:SW, L2:1)

This means C5 is effectively between BOOT drive and SW, with R9 in series from BOOT to the capacitor. Do not short BOOT and SW.

Buck output BUCK_5V

Connect these together:

L2:2
C3:1
C4:1
F2:1
R6:1

Connect output capacitor returns:

C3:2 -> GND
C4:2 -> GND

Feedback FB

Connect these together:

U2:FB
R6:2
R7:P1

Then:

R6:1 -> BUCK_5V
R7:P2 -> GND

3. Buck output to Raspberry Pi through fuse/eFuse

The corrected topology is: BUCK_5V -> F2 -> U1_IN -> U1 eFuse -> PI_5V -> H1 pins 2 and 4.

BUCK_5V to fuse

F2:1 -> BUCK_5V

eFuse input U1_IN

Connect these together:

F2:2
U1:3
U1:4
U1:EN/UVLO

This makes the eFuse enabled when the buck output is present. If you later want undervoltage lockout tuning, replace this direct tie with the datasheet divider network.

eFuse output PI_5V

Connect these together:

U1:OUT
H1:Pin_2
H1:Pin_4
D1:1 if D1 is the PI_5V TVS/clamp node

Ground side of PI_5V clamp:

D1:2 -> GND

eFuse ILM

Connect:

U1:ILM -> R_ILM:P1
R_ILM:P2 -> GND

Current metadata target: R_ILM = 1.0 kOhm, about 2.04 A using ILIMIT = 2000/RILM + 0.04.

eFuse dVdt and FLT options

If you want to eliminate floating ERC warnings:

Preferred implementation:

Add/keep C7 = 3.3 nF.
Connect U1:dVdt -> C7:P1.
Connect C7:P2 -> GND.
Add/keep R10 = 100 kOhm.
Connect U1:~FLT -> R10:P1.
Connect R10:P2 -> PI_5V.

Alternative if intentionally unused:

Mark U1:dVdt and U1:~FLT as No Connect only if the TPS259531 datasheet allows those pins to float in your configuration.

4. Motor channel 1 low-side switch

Channel 1 uses Q1 and connector J2 based on the current net mapping.

Motor power

J2:P2 -> VIN_6V motor positive
J2:P1 -> MOTOR1_LOW motor negative/switched node

Low-side switch node MOTOR1_LOW

Connect these together:

J2:P1
Q1:D
D2:A

MOSFET source

Q1:S -> GND

Flyback diode orientation

D2:K -> VIN_6V
D2:A -> MOTOR1_LOW

The cathode must be on raw 6 V; the anode must be on the motor negative/MOSFET drain node.

Gate drive

PWM10 source net:

H1:Pin_19 -> R1:1

Q1_GATE net:

R1:2
R3:1
Q1:G

Pulldown:

R3:2 -> GND

5. Motor channel 2 low-side switch

Channel 2 uses Q2 and connector J1 based on the current net mapping.

Motor power

J1:P2 -> VIN_6V motor positive
J1:P1 -> MOTOR2_LOW motor negative/switched node

Low-side switch node MOTOR2_LOW

Connect these together:

J1:P1
Q2:D
D3:A

MOSFET source

Q2:S -> GND

Flyback diode orientation

D3:K -> VIN_6V
D3:A -> MOTOR2_LOW

Gate drive

PWM17 source net:

H1:Pin_11 -> R2:2

Q2_GATE net:

R2:1
R4:1
Q2:G

Pulldown:

R4:2 -> GND

Note: R2 orientation is opposite R1 in the current mapping. That is electrically OK for a resistor. If you want visual consistency, you may swap the naming later, but electrically it is fine as long as one side is PWM17 and the other side is Q2_GATE.

6. LED GPIO JST connectors

These are GPIO-plus-ground only. They are suitable only for LED modules that already include current limiting.

GPIO24 LED connector

Connect:

H1:Pin_18 -> J5:Pin_1 on net GPIO24_LED
J5:Pin_2 -> GND

GPIO25 LED connector

Connect:

H1:Pin_22 -> J7:Pin_1 on net GPIO25_LED
J7:Pin_2 -> GND

If connecting bare LEDs directly, add series resistors or a transistor/MOSFET driver. Do not connect bare LEDs directly to GPIO without current limiting.

7. Test point TP3

Current issue: TP3 is a single-pin net on Net 22.

Choose one:

If TP3 is meant to probe a real signal, connect TP3 to that intended net, such as BUCK_5V, PI_5V, VIN_6V, PWM10, or PWM17.
If TP3 is not needed, remove it.
If TP3 is intentionally a standalone mechanical/test pad, mark it intentionally No Connect if the tool supports that.

8. Final ERC checklist

After wiring, verify these exact conditions:

VIN_6V contains J6:A, U2:VIN, U2:EN, input cap positives, motor positives, and flyback cathodes.
GND is a single common ground containing J6:B, Pi GND pins, U2 GND, U1 GND/EP, MOSFET sources, cap returns, resistor pulldowns, and LED connector pin 2s.
SW contains exactly U2:SW, L2:1, C5:P2.
Bootstrap path is U2:BOOT -> R9 -> C5:P1, and C5:P2 -> SW.
BUCK_5V contains L2:2, C3:1, C4:1, F2:1, R6:1.
FB contains U2:FB, R6:2, R7:P1; R7:P2 is GND.
U1_IN contains F2:2, U1:3, U1:4, U1:EN/UVLO.
PI_5V contains U1:OUT, H1:Pin_2, H1:Pin_4, and the PI_5V clamp node if used.
MOTOR1_LOW contains J2:P1, Q1:D, D2:A.
MOTOR2_LOW contains J1:P1, Q2:D, D3:A.
PWM10 is H1:Pin_19 -> R1:1; Q1_GATE is R1:2 + R3:1 + Q1:G; R3:2 is GND.
PWM17 is H1:Pin_11 -> R2:2; Q2_GATE is R2:1 + R4:1 + Q2:G; R4:2 is GND.
GPIO24_LED is H1:Pin_18 -> J5:Pin_1; J5:Pin_2 is GND.
GPIO25_LED is H1:Pin_22 -> J7:Pin_1; J7:Pin_2 is GND.
J6:C is No Connect unless plug detect is intentionally implemented.
U1:dVdt, U1:~FLT, and TP3 are either wired as described or intentionally marked No Connect.

Notes on connection syntax

When using Flux connection operations, pin IDs should be written as Ref:Pin, for example U2:SW, L2:1, C5:P2, and existing named nets are referenced as ^NetName. Ground nets can be referenced as ^GND; non-ground nets should be created or verified before referencing them by name. This follows the Flux connection syntax guidance. See the retrieved connection-syntax guidance for details.

0. Cleanup before wiring

1. Barrel jack and raw 6 V rail

`VIN_6V`

`GND`

No connect

2. TPS56339 buck converter U2

Buck input

Switch node `SW`

Bootstrap network with R9

Buck output `BUCK_5V`

Feedback `FB`

3. Buck output to Raspberry Pi through fuse/eFuse

`BUCK_5V` to fuse

eFuse input `U1_IN`

eFuse output `PI_5V`

eFuse ILM

eFuse dVdt and FLT options

4. Motor channel 1 low-side switch

Motor power

Low-side switch node `MOTOR1_LOW`

MOSFET source

Flyback diode orientation

Gate drive

5. Motor channel 2 low-side switch

Motor power

Low-side switch node `MOTOR2_LOW`

MOSFET source

Flyback diode orientation

Gate drive

6. LED GPIO JST connectors

GPIO24 LED connector

GPIO25 LED connector

7. Test point TP3

8. Final ERC checklist

Notes on connection syntax

Reviews

Documents

Schematic Text Mapping for Other LLMs

Manual Wiring Instructions - Pi Zero 2 W Power HAT

Schematic Audit — Check My Work

Assets

No assets added.

Project Name

Stuck Cyan Lightcycle 92e7

Description

Pi Zero 2 W Power HAT – 6 V Input, 5.2 V Buck to Pi 5 V Header via 1.85 A Fuse, Enhanced Input & Pi Rail Protection (TVS + High-Hold PTC + 5 A Schottky)

Properties

Audit Report

Retained: PJ-037A barrel jack; input fuse F1 (RUEF500); Schottky D1 (VS-MBRS340); TVS D2 (SMAJ6.0A); buck converter U1 (TPS56339DDC) with L1 (4.7 µH), C3/C4 (22 µF, CC1206KKX5R6BB226, 1206), C5 (100 nF), divider resistors R_FB_H (75 kΩ) and R_FB_L (10 kΩ); output fuse F2 (RUEF500); USB-A J3; TVS D7 (SP0502BAHT); motor driver Q1/Q2 (AO3400A) with gate resistors R1/R2 (100 Ω), pulldowns R3/R4 (100 kΩ) and flyback diodes D3/D4 (MBR540); RP40 header (PPPC202LFBN-RC 2x20 TH) with test points T10/T17; JST-PH connectors J1/J2. Removed: duplicate net portals; ESD diodes D5 and D6. Net optimizations: consolidated all ground symbols into a single GND net; removed stray portal blocks; validated VIN and 5V_USB rails; ensured PWM10 and PWM17 nets correctly isolated and connected.

Net Type

Power

Prune Report

Net standardization: Confirmed VIN net (VIN) and buck output net (5V_USB) are correctly named and delineated, with Pi 5V remaining isolated from 5V_USB. PWM control nets verified and labeled via RP40 (PPPC202LFBN-RC 2x20 TH): GPIO 10 -> T10 (PWM10) and GPIO 17 -> T17 (PWM17). Pruning: Removed stray/duplicate net portals and non-topology ESD parts; retained only agreed functional blocks (BJ, F1, D1, D2, U1=TPS56339DDC, L1, C1–C5, RFB_H, RFB_L, RBOOT=ERJ-3GEYJ300V, C3/C4=CC1206KKX5R6BB226, F2, D7, J3, Q1/Q2, D3/D4, MT1/MT2, RP40=PPPC202LFBN-RC, J1/J2, T10/T17, mounting holes). Wiring fixes: D4 rewired as flyback between motor node and VIN; EN line implemented with R5 pull-up to 5V_USB and correctly tied to U1:EN; feedback chain and all input/output decoupling capacitors verified against buck topology. Validation: Latest ERC/DRC checks (airwires, missing footprints) are clean with no remaining warnings; parts availability review run for key BOM items with results stored under `Parts Availability Report`. Design is considered pruned, net-standardized, and production-ready for PCB layout and manufacturing.

Parts Av…ed Types

parts_available

Project Description

Pi Zero 2 W Power HAT – Buck Converter Feeds Pi 5V Header via ~1.85 A PTC Fuse (USB Power Output Removed)

Airwire Nets

[]

Net: BUC…et Type

Power

Parts Av…y Report

{"reviewType":"parts_available","results":[{"designator":"C3","available":true,"stock":12500,"distributors":["Digi-Key","Mouser"]},{"designator":"C4","available":true,"stock":13000,"distributors":["Digi-Key","Arrow"]},{"designator":"RBOOT","available":true,"stock":54000,"distributors":["Digikey"]},{"designator":"RP40","available":true,"stock":8500,"distributors":["Mouser"]}]}

Final Ver…n Report

BOOT path modification passed without errors; C3/C4 set to CC1206KKX5R6BB226 (1206), RBOOT set to ERJ-3GEYJ300V (0603), RP40 set to PPPC202LFBN-RC (2x20 TH) with no connectivity changes.

Feedback…t Value

55000

System Architecture

Diagram

ERC/DRC Report

ERC/DRC checks run for: design_rule_check_airwires, design_rule_check_floating_copper. No remaining warnings.

PTC Replacements

F1 (1206L050/15YR): HoldCurrent 0.5 A, Package 1206; F2 (ASMD1206-200): HoldCurrent 1.85 A, Package 1206

Voltage

5.2

Net

BUCK_5V

Net: PiVI…Net Type

Power

Domain

Consumer Electronics

ERC/DRC…d Types

design_rule_check_airwires, design_rule_check_floating_copper

DRC Report

ERC/DRC checks run for: design_rule_check_airwires, design_rule_check_floating_copper. No remaining warnings.

System Architecture

Diagram

Protecti…umented

Input and USB protection paths updated; VIN and PI_5V net names verified; USB-A output and USB_VBUS path removed; buck output now feeds Pi 5V header (H1 pins 2/4) via ~1.85 A PTC fuse F2 with common GND, maintaining ~5.2 V BUCK_5V output.

5V_USB i…nfirmed

Revised: USB-A VBUS path removed; buck output BUCK_5V now routed through ~1.85 A PTC F2 onto PI_5V (H1 pins 2/4). Previous 5V_USB isolation note superseded by new topology.

ERC/DRC…d Types

design_rule_check_airwires, design_rule_check_floating_copper

Manufact…fenders

Buck Out… Voltage

5.2

ERC/DRC Status

Clean

Floating…rIslands

[]

Part Type

Portal

Board Size

65.0 mm x 30.0 mm

Manufact… Target

ERC/DRC Report

ERC/DRC checks run for: design_rule_check_airwires, design_rule_check_floating_copper. No remaining warnings.

Net: VIN …Net Type

Power

Feedback…) Value

10000

License

solderpad.org/licenses/SHL-2.1/

Pricing & Availability

Distributor	Qty 1
Arrow	$2.51–$3.01
Digi-Key	$1.98–$3.39
LCSC	$3.43–$3.79
Mouser	$3.14–$3.44
TME	$1.46
Verical	$1.58–$91.06

Controls

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