Raspberry Pi Zero HAT PCB Design

flux

Work done
  • Re-audited the live schematic against the remaining plan.
  • Added the missing eFuse support parts: C7 = 3.3 nF for U1:dVdt and R10 = 100 kΩ for U1:~FLT pull-up.
  • Confirmed current remaining schematic issues: L2:1 is still floating, J2:P1 is still floating, U1:dVdt/U1:~FLT and new C7/R10 are not yet wired, J6:C still needs explicit NC, TP3 remains a single-pin net, and 41 Net Portals remain.
  • Updated the handoff mapping with the current blocked state and exact intended repairs: Schematic Text Mapping for Other LLMs.
Success criteria review
  • ✅ Verified existing corrected intent for VIN_6V, BUCK_5V, PI_5V, motors, LED GPIO JSTs, common GND, and feedback values.
  • ✅ Added C7 and R10 parts needed for the eFuse omissions.
  • ❌ Could not safely apply final wiring repairs due to a schematic data issue that is blocking edits.
  • ❌ ERC is not clean yet; remaining warnings include L2:1, J2:P1, U1:dVdt, U1:~FLT, C7, R10, J6:C, TP3, and expected unused Pi header pins.
  • ❌ PCB layout preparation should wait until the schematic edit issue is cleared and the final schematic repairs are verified.
Next steps
Clear the schematic edit issue, then apply the documented repairs: connect L2:1 to U2:SW/C5:P2, connect J2:P1 to MOTOR1_LOW, wire C7 and R10, mark J6:C NC, resolve TP3, remove stale portals, then rerun ERC/DRC before PCB layout setup.
bubbaa

bubbaa

give a text instructions of exactly what to wire but dont wire yourself.

flux

I created a detailed copy-pasteable wiring checklist here: Manual Wiring Instructions - Pi Zero 2 W Power HAT.
It lists the exact pin-to-pin/net wiring for VIN_6V, GND, TPS56339 buck/BOOT/SW/FB, TPS259531 eFuse, motor MOSFET channels, LED JSTs, TP3, and the final ERC checklist.
bubbaa

bubbaa

I think I wired everything. check my work. do not wire anything yourself but call out what is needed.

flux

Your main functional wiring looks mostly correct now: VIN_6V, buck/eFuse-to-PI_5V, motor low-side switching, LED GPIO connectors, and common GND are all largely in place. Remaining issues are cleanup/ERC hygiene: label the unnamed VIN_6V, BUCK_5V, and GND nets, rename AUTO_NAME to Q2_GATE, mark J6:C NC, resolve/assign TP1–TP4 and 6V:P1, then route the PCB airwires. Full audit is in Schematic Audit — Check My Work.
Run ERC/DRC
List net labels
Check BOM completeness
Inspect airwires
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Files

Schematic

Layout

Preview

F2
C2 P2 - C3 2
C4 2 - C6 2
C4 2 - C6 2
C3 2 - H1 Pin_34
U1 GND - U1 EP
C4 2 - C6 2
U2 GND - H1 Pin_6
J7 Pin_2 - D1 2
C4 2 - C6 2
C4 2 - C6 2
C4 2 - C6 2
U1 GND - U1 EP
C4 2 - C6 2
J7 Pin_2 - D1 2
C4 2 - C6 2
J5 Pin_2 - D1 2
U1 GND - U1 EP
J6 A - D3 K
J6 B - U2 GND
J6 A - D3 K
J6 B - U2 GND
J6 B - U2 GND
J6 B - H1 Pin_9
C4 2 - C6 2
C4 2 - C6 2
C4 2 - C6 2
C2 P2 - C3 2
C4 2 - C6 2
C4 2 - C6 2
J6 B - H1 Pin_9
C4 2 - C6 2
C4 2 - C6 2
J7 Pin_2 - D1 2
J6 A - D3 K
J7 Pin_2 - D1 2
C4 1 - F2 1
H1 Pin_18 - J5 Pin_1
H1 Pin_19 - R1 1
U1 OUT - H1 Pin_2
Q1 D - D2 A
H1 Pin_22 - J7 Pin_1
J6 A - U2 VIN
C2 P1 - C6 1
U2 FB - R6 2
H1 Pin_22 - J7 Pin_1
R9 2 - C5 P1
U2 SW - L2 1
H1 Pin_11 - R2 2
F2 2 - U1 IN
F2 2 - U1 IN
C2 P1 - C6 1
C4 1 - F2 1
J6 A - U2 VIN
J6 A - U2 VIN
J6 A - U2 VIN
Q2 D - D3 A
J1 P2 - J2 P2
C2 P1 - C6 1
L2 2 - C3 1
Q1 D - D2 A
U1 OUT - H1 Pin_2
R9 2 - C5 P1
H1 Pin_4 - D1 1
C2 P1 - C6 1
L2 2 - C3 1
U2 FB - R6 2
U1 OUT - H1 Pin_2
H1 Pin_19 - R1 1
Q2 D - D3 A
H1 Pin_4 - D1 1
U1 OUT - H1 Pin_2
C4 1 - F2 1
H1 Pin_18 - J5 Pin_1
J1 P2 - J2 P2
U2 SW - L2 1
H1 Pin_11 - R2 2
C2 P1 - C6 1
R4
J2
Hole3
6V
6V
C1
Capacitance
10µF
U1
Hole2
6V
R3
6V
6V
6V
Hole4
6V
J1
6V
Hole1
C7
Capacitance
3.3nF
J6
Manufacturer Part Number
54-00166
TP4
J5
R7
Resistance
10000 Ω
D2
D1
R1
R10
Resistance
100kΩ
TP2
TP3
C4
C5
End of Life
Capacitance
0.1uF
C2
End of Life
Capacitance
0.1uF
R2
TP5
C3
H1
Manufacturer Part Number
2.54-2*20
J7
TP1
D3
R_ILM
Resistance
1000 Ω
C6
L2
R6
Resistance
76800 Ω
Q2
Q1
D5
R9
U2
Schematic Text Mapping for Other LLMs
Project intent
Raspberry Pi Zero 2 W HAT corrected topology:
  • Tensility 54-00166 barrel jack input with J6:A = VIN_6V, J6:B = GND, and J6:C = NC / unused switch contact.
  • U2 = TPS56339DDCR buck regulator converts raw 6 V to about 5.2 V.
  • Buck output BUCK_5V powers the Raspberry Pi 5 V header through F2 and the U1 = TPS259531DSGT eFuse/protection stage.
  • Motors remain on raw VIN_6V and are switched with low-side N-MOSFETs.
  • All grounds are common.
  • LED connectors J5 and J7 expose only GPIO24/GPIO25 plus GND and are for LED modules with built-in current limiting unless additional series resistors/drivers are added.
Important designator convention
Current schematic uses:
  • U2 = TPS56339DDCR buck regulator.
  • U1 = TPS259531DSGT eFuse / protection IC for the Pi 5 V rail.
  • H1 = Raspberry Pi 40-pin header.
  • J6 = Tensility barrel jack.
Current verified net mapping
VIN_6V raw 6 V rail
Expected corrected mapping:
  • J6:A
  • U2:VIN
  • U2:EN
  • C1:P1, C2:P1, C6:1
  • D5:K VIN TVS cathode
  • D2:K, D3:K flyback diode cathodes
  • J2:P2, J1:P2 motor positive pins
GND common ground
Expected corrected mapping:
  • J6:B
  • U2:GND
  • U1:GND, U1:EP
  • Raspberry Pi ground pins including H1:Pin_6, H1:Pin_9, H1:Pin_14, H1:Pin_25, H1:Pin_34, H1:Pin_39
  • Q1:S, Q2:S
  • R3:2, R4:2, R7:P2, R_ILM:P2
  • C1:P2, C2:P2, C3:2, C4:2, C6:2
  • D5:A, D1:2
  • J5:Pin_2, J7:Pin_2
Buck regulator U2 / TPS56339
  • Input: U2:VIN -> VIN_6V; U2:EN -> VIN_6V for always-on operation.
  • Ground: U2:GND -> GND.
  • Switch node should be SW = U2:SW + L2:1 + C5:P2.
  • Bootstrap path should be U2:BOOT -> R9:1 -> R9:2 -> C5:P1 -> C5:P2 -> SW.
  • Output: BUCK_5V = L2:2 + C3:1 + C4:1 + F2:1 + R6:1.
  • Output capacitors: C3:2, C4:2 -> GND.
  • Feedback: FB = U2:FB + R6:2 + R7:P1; R7:P2 -> GND.
  • Feedback values: R6 = 76.8 kΩ, R7 = 10 kΩ, target BUCK_5V ≈ 5.2 V using the project’s ~0.6 V FB reference assumption.
Current caveat from latest audit
A post-cleanup verification showed the SW connection still needs one final repair: U2:SW and C5:P2 are together, but L2:1 is not visible on that same net. The intended required connection is still U2:SW = C5:P2 = L2:1.
Current edit blocker
Recent direct schematic edit attempts are blocked by a stale/malformed internal node reference left over from the earlier Net Portal corruption. Connection edits and Net Portal deletion attempts currently fail before they can be applied. Do not treat this as a topology contradiction; the intended repairs below remain valid and should be applied once the stale node is cleared.
Pi 5 V path through eFuse
  • BUCK_5V -> F2:1
  • F2:2 -> U1_IN
  • U1_IN = F2:2 + U1:IN pins + U1:EN/UVLO
  • PI_5V = U1:OUT + H1:Pin_2 + H1:Pin_4 + D1:1
  • D1:2 -> GND
  • R_ILM = 1.0 kΩ from U1:ILM to GND; using ILIMIT = 2000/RILM + 0.04, this programs approximately 2.04 A.
  • U1:dVdt and U1:~FLT were flagged by ERC as floating. C7 = 3.3 nF and R10 = 100 kΩ were added to the schematic, but their connections could not be verified/applied because of the stale-node edit blocker. Intended final wiring: C7:P1 -> U1:dVdt, C7:P2 -> GND, R10:P1 -> U1:~FLT, R10:P2 -> PI_5V.
Motor channel 1
  • VIN_6V -> J2:P2 motor positive.
  • MOTOR1_LOW = J2:P1 + Q1:D + D2:A.
  • Q1:S -> GND.
  • Flyback: D2:K -> VIN_6V, D2:A -> MOTOR1_LOW.
  • Control: PWM10 = H1:Pin_19 + R1:1.
  • Gate: Q1_GATE = R1:2 + R3:1 + Q1:G.
  • Pulldown: R3:2 -> GND.
Motor channel 2
  • VIN_6V -> J1:P2 motor positive.
  • MOTOR2_LOW = J1:P1 + Q2:D + D3:A.
  • Q2:S -> GND.
  • Flyback: D3:K -> VIN_6V, D3:A -> MOTOR2_LOW.
  • Control: PWM17 = H1:Pin_11 + R2:2.
  • Gate net is electrically Q2_GATE = R2:1 + R4:1 + Q2:G; the live schematic may still display this as AUTO_NAME due to a duplicate/colliding label.
  • Pulldown: R4:2 -> GND.
  • Note: R2 is a two-terminal series resistor, so the orientation PWM17 -> R2:2 and R2:1 -> Q2_GATE is electrically valid.
LED module connectors
  • GPIO24_LED = H1:Pin_18 + J5:Pin_1; J5:Pin_2 -> GND.
  • GPIO25_LED = H1:Pin_22 + J7:Pin_1; J7:Pin_2 -> GND.
  • These are GPIO + GND only. Use only with LED modules that already include current limiting; bare LEDs require series resistors or a transistor/MOSFET driver.
Machine-readable mapping
Yaml
designators:
  pi_header: H1
  barrel_jack: J6
  buck_regulator: U2
  efuse: U1
  buck_inductor: L2
  buck_boot_resistor: R9
  buck_boot_capacitor: C5
  buck_feedback_high: R6
  buck_feedback_low: R7
  buck_output_caps: [C3, C4]
  efuse_input_fuse: F2
  motor1_connector: J2
  motor2_connector: J1
  motor1_mosfet: Q1
  motor2_mosfet: Q2
  motor1_flyback: D2
  motor2_flyback: D3
  led_gpio24_connector: J5
  led_gpio25_connector: J7

nets:
  VIN_6V:
    - J6:A
    - U2:VIN
    - U2:EN
    - C1:P1
    - C2:P1
    - C6:1
    - D5:K
    - D2:K
    - D3:K
    - J2:P2
    - J1:P2
  GND:
    - J6:B
    - U2:GND
    - U1:GND
    - U1:EP
    - H1:Pin_6
    - H1:Pin_9
    - H1:Pin_14
    - H1:Pin_25
    - H1:Pin_34
    - H1:Pin_39
    - Q1:S
    - Q2:S
    - R3:2
    - R4:2
    - R7:P2
    - R_ILM:P2
    - C1:P2
    - C2:P2
    - C3:2
    - C4:2
    - C6:2
    - D5:A
    - D1:2
    - J5:Pin_2
    - J7:Pin_2
  SW_intended:
    - U2:SW
    - L2:1
    - C5:P2
  BOOT:
    - U2:BOOT
    - R9:1
  BOOT_CAP:
    - R9:2
    - C5:P1
  BUCK_5V:
    - L2:2
    - C3:1
    - C4:1
    - F2:1
    - R6:1
  FB:
    - U2:FB
    - R6:2
    - R7:P1
  U1_IN:
    - F2:2
    - U1:IN
    - U1:EN/UVLO
  PI_5V:
    - U1:OUT
    - H1:Pin_2
    - H1:Pin_4
    - D1:1
  PWM10:
    - H1:Pin_19
    - R1:1
  Q1_GATE:
    - R1:2
    - R3:1
    - Q1:G
  MOTOR1_LOW:
    - J2:P1
    - Q1:D
    - D2:A
  PWM17:
    - H1:Pin_11
    - R2:2
  Q2_GATE:
    - R2:1
    - R4:1
    - Q2:G
  MOTOR2_LOW:
    - J1:P1
    - Q2:D
    - D3:A
  GPIO24_LED:
    - H1:Pin_18
    - J5:Pin_1
  GPIO25_LED:
    - H1:Pin_22
    - J7:Pin_1
Remaining verification / repair notes
  1. Clear the stale/malformed node edit blocker, then restore/verify L2:1 on SW with U2:SW and C5:P2.
  2. Confirm J6:C is physically marked no-connect; the design intent is NC unless used for plug detect.
  3. Wire the newly added eFuse support parts: C7:P1 -> U1:dVdt, C7:P2 -> GND, R10:P1 -> U1:~FLT, R10:P2 -> PI_5V.
  4. Connect J2:P1 to MOTOR1_LOW if it is still reported floating; intended MOTOR1_LOW = J2:P1 + Q1:D + D2:A.
  5. Optional cleanup: rename the Q2 gate net from AUTO_NAME to Q2_GATE after removing any duplicate/colliding label.
  6. Layout stage must use wider copper for VIN_6V, motor paths, BUCK_5V, and PI_5V, and keep buck SW/BOOT loops short.

  • Project intent

  • Important designator convention

  • Current verified net mapping

  • VIN_6V raw 6 V rail

  • GND common ground

  • Buck regulator U2 / TPS56339

  • Current caveat from latest audit

  • Current edit blocker

  • Pi 5 V path through eFuse

  • Motor channel 1

  • Motor channel 2

  • LED module connectors

  • Machine-readable mapping

  • Remaining verification / repair notes