LED Blinker Circuit Design

flux

Manufacturing files generated successfully:
  1. Gerber ZIP
  2. https://cdn2.flux.ai/flux-comment-files/files/commentFileId-0fcb9cebade9136f20aa75363445c0678a6467a5900e4c7ae97399cb41610659.csv?GoogleAccessId=autopilot-sa-d60c62b%40graviton-mvp.iam.gserviceaccount.com&Expires=4935217148&Signature=qxIdw2muNMkvlxRMQDsxXiRWAJ6D1V0ojJJjYrOFn5b4qANEr5Nzlr3AiOVkuuJxozNbHUCd3imPJpt7JKCutVaat05Lc7zahP395b6QvxEq8BRSVvAw72uDkGHd57jB%2BDuJzknkedn7csdAm5KlP%2BsiZvk1VSkmtFb3ENVCaYVwU5LgUKXKcWc4qSWTSb4xQa5LY2s29OgeWYEXDoFJnGfk2KOm2vn1Pjx6CF6tNhLkCsWEA%2FwSP0OrtR2qRUZS5mzsL73XV4J3HkhrnrLGk%2B6IP3eEx7Iu6eZNuM0jX64BkZaYvxU52CuOgCI3VhVD%2Ba9mcNwTwXjMMmUAp7skUQ%3D%3D
  3. https://cdn2.flux.ai/flux-comment-files/files/commentFileId-d0f0f0a9d255f45deb56cd5b33d0f22abe06e385384e741c4f488a7a9345be39.csv?GoogleAccessId=autopilot-sa-d60c62b%40graviton-mvp.iam.gserviceaccount.com&Expires=4935217149&Signature=lC3VinI9geHZQwGJ7Ge2QdBYK8UhZc%2Bc5jm0fr%2BTIyjv87yVCO1dUA0VS1yW2h6lEf4GlxvBLI0x%2BfOCtjJtxFFd6dAFFQMRUr1JjZi8mIGivrsOQ4QgWITpHazDhX9hrWBu4U%2BrYrVZNX7R%2BvSv%2B7npOzOH9IPzMeMvLCYdAA3GkB44Gk5P41pTmkJTr%2FaYxvZrlwzNbaCZdavhl9kpkmY6ZRJquFw2Jl9kVBikUIni3YCHLB%2FwMxAyVLAwFBExBif2O27zfhSc%2BD0MTzLjqzHVhgB9c1b0awXGpM%2FyTN%2FtJ5T9RWAjflGG1F0Skni%2BJUxyk7lHBBurvUZqjIOYmg%3D%3D
  4. https://cdn2.flux.ai/flux-comment-files/files/commentFileId-5e25aba74de45ca8f45a42cc4239d11e1da914de457f4cfca86c2e678f2b0b43.csv?GoogleAccessId=autopilot-sa-d60c62b%40graviton-mvp.iam.gserviceaccount.com&Expires=4935217149&Signature=YDf8QeeXJPhw%2Fh4Jbl0OfHV1Scece1LoJX7CNSWmBpLsTKVqR1EEibuIMHY3FZwQv5hJ%2BIPNHp2BeWDLLLH%2B%2FILBmjREk65YWuQhRgid%2Bwfz9QtgRbylToFJq96JjRbL3sf%2BzBszxj8zg4jsR%2BxHhjdVvKuCTmwjfGJsW9Xr2bC8sn17AW8GumxxmilV0gJ2GfK8wCaQHLxXD5nwqRyOYGLarJCCvHLBCBCvix0yyQyZUpHnowuXarDOIUKZZ3vXInWn%2FKbyEDO7VPUH5N4sfbb39WzfnoPgKs6FrWBhWgbusD4DDYnHwcdTKSWkST1La%2BQMm8%2BThI0n4lPAQGUwAw%3D%3D

  5. DXF Drawing

    Failed to load DXF drawing.
The DXF uses a MILLING_CUTOUT layer and shows the 1.5mm non-plated full-height isolation slot centered at x=85mm on the 200×140mm board. Specify 2-layer FR4, ENIG in the fab order notes.
Review package and DRC
Review Gerbers
Check DXF alignment
Run final reports
Regenerate after manual routes
U_MCU
U_3V3
J_SIM
U_5V
J_S2
U_LTE
J_S1
U_4V
K1 COIL2 - D2 anode
U_MCU PB2 - U_LTE STATUS
J_PWR ~ - U_5V GND
U_MCU PA14 - J_SWD 04
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V VIN
J_PWR ~ - U_5V VIN
U_MCU VDD - C_MCU_VDD1 P1
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_MCU PB9 - J_DHT22 Pin_2
C_NRST P2 - R_BOOT0 P2
K1 COM - J_RELAY_CONTACT ~
J_PWR ~ - U_5V VIN
J_S2 ~ - U_OPTO2 ~
K1 NO - J_RELAY_CONTACT ~
U_MCU VDD - C_MCU_VDD1 P1
J_PWR ~ - U_5V GND
U_LTE VBAT - U_LTE VBAT__1
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_MCU PA2 - U_LTE RXD
J_PWR ~ - U_5V GND
U_MCU PB1 - U_LTE ~RESET
U_4V SW - L1 P1
C_MCU_VDD1 P2 - C_MCU_VDD2 P2
J_S2 ~ - U_OPTO2 ~
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
K1 NO - J_RELAY_CONTACT ~
U_LTE USIM1_RST - J_SIM RST
C_MCU_VDD1 P2 - C_MCU_VDD2 P2
J_S2 ~ - R_OPTO_LED2 P1
U_MCU PB10 - R_OPTO_LED P1
U_MCU VDD - C_MCU_VDD1 P1
J_S2 ~ - U_OPTO2 ~
R_STATUS P2 - D_STATUS +
J_PWR ~ - U_5V GND
U_MCU PB5 - R_STATUS P1
U_LTE USIM1_DATA - J_SIM I/O
U_LTE USIM1_VDD - J_SIM VCC
J_PWR ~ - U_5V GND
U_MCU PD0 - Y1 1
U_4V SW - L1 P1
J_PWR ~ - U_5V GND
U_LTE USIM1_DET - J_SIM DETECTION_SWITCH
R_OPTO_LED2 P2 - U_OPTO2 ~
U_MCU PB1 - U_LTE ~RESET
K1 COIL2 - D2 anode
R_FB1 P2 - R_FB2 P1
U_MCU PB6 - J_OLED 3
U_MCU PA10 - J_UART Pin_2
U_ACS VOUT - U_MCU PA0
U_MCU PB0 - U_LTE ~PWRKEY
R_Q_BASE P2 - Q1 B
U_LTE VBAT - U_LTE VBAT__1
U_MCU PD1 - Y1 3
U_MCU VBAT - C_MCU_VDDA P1
U_MCU VDD - C_MCU_VDD1 P1
J_PWR ~ - U_5V GND
U_MCU PA3 - U_LTE TXD
J_PWR ~ - U_5V GND
U_LTE USIM1_DET - J_SIM DETECTION_SWITCH
J_PWR ~ - U_5V GND
U_LTE USIM1_DATA - J_SIM I/O
U_MCU PA9 - J_UART Pin_1
U_5V TAB(VOUT) - U_3V3 VIN
U_MCU NRST - R_NRST P2
U_4V VCC - C_4V_VCC P1
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_MCU BOOT0 - R_BOOT0 P1
C_NRST P2 - R_BOOT0 P2
J_PWR ~ - U_5V GND
U_MCU PB2 - U_LTE STATUS
U_4V VCC - C_4V_VCC P1
J_S2 ~ - R_OPTO_LED2 P1
U_MCU PA10 - J_UART Pin_2
U_OPTO1 ~ - R_Q_BASE P1
U_MCU VBAT - C_MCU_VDDA P1
R_Q_BASE P2 - Q1 B
R_FB1 P2 - R_FB2 P1
J_PWR ~ - U_5V GND
R_STATUS P2 - D_STATUS +
J_PWR ~ - U_5V GND
U_MCU VDD - C_MCU_VDD1 P1
J_PWR ~ - U_5V GND
U_ACS FILTER - C_ACS_FILTER P1
J_PWR ~ - U_5V GND
U_MCU VDD - C_MCU_VDD1 P1
U_LTE USIM1_RST - J_SIM RST
J_PWR ~ - U_5V GND
R_OPTO_LED P2 - U_OPTO1 ~
U_MCU VDD - C_MCU_VDD1 P1
U_OPTO1 ~ - R_Q_BASE P1
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_LTE USIM1_CLK - J_SIM CLK
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_LTE VBAT - U_LTE VBAT__1
J_PWR ~ - U_5V GND
U_LTE RF_ANT - J_ANT SIG
J_PWR ~ - U_5V GND
J_S2 ~ - U_OPTO2 ~
J_PWR ~ - U_5V GND
U_ACS VOUT - U_MCU PA0
U_4V BOOT - C_4V_BOOT P1
U_LTE USIM1_CLK - J_SIM CLK
K1 COIL2 - D2 anode
J_PWR ~ - U_5V GND
U_4V BOOT - C_4V_BOOT P1
J_PWR ~ - U_5V GND
U_MCU PB5 - R_STATUS P1
U_OPTO2 ~ - U_MCU PB8
J_PWR ~ - U_5V GND
J_SIM GROUND_3 - J_ANT GND
C_MCU_VDD1 P2 - C_MCU_VDD2 P2
U_LTE VBAT - U_LTE VBAT__1
U_MCU PD0 - Y1 1
U_MCU NRST - R_NRST P2
U_MCU PA13 - J_SWD 02
U_LTE VBAT - U_LTE VBAT__1
J_PWR ~ - U_5V GND
C_MCU_VDD1 P2 - C_MCU_VDD2 P2
J_CT ~ - U_MCU PA1
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_5V TAB(VOUT) - U_3V3 VIN
J_PWR ~ - U_5V GND
U_MCU PB9 - J_DHT22 Pin_2
K1 COM - J_RELAY_CONTACT ~
J_VSENSE ~ - U_MCU PA4
U_OPTO1 ~ - R_Q_BASE P1
U_LTE RF_ANT - J_ANT SIG
U_5V TAB(VOUT) - U_3V3 VIN
U_LTE USIM1_VDD - J_SIM VCC
U_MCU PB0 - U_LTE ~PWRKEY
U_MCU NRST - R_NRST P2
J_SIM GROUND_3 - J_ANT GND
U_OPTO2 ~ - U_MCU PB8
R_OPTO_LED2 P2 - U_OPTO2 ~
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_4V SW - L1 P1
K1 NC - J_RELAY_CONTACT ~
U_MCU BOOT0 - R_BOOT0 P1
U_MCU PA2 - U_LTE RXD
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_CT ~ - U_MCU PA1
K1 NC - J_RELAY_CONTACT ~
U_LTE VBAT - U_LTE VBAT__1
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
R_OPTO_LED P2 - U_OPTO1 ~
J_PWR ~ - U_5V VIN
U_MCU VBAT - C_MCU_VDDA P1
J_PWR ~ - U_5V GND
U_ACS FILTER - C_ACS_FILTER P1
J_VSENSE ~ - U_MCU PA4
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_MCU PB10 - R_OPTO_LED P1
U_MCU PA13 - J_SWD 02
U_MCU PB7 - J_OLED 4
J_PWR ~ - U_5V GND
U_5V TAB(VOUT) - U_3V3 VIN
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_MCU NRST - R_NRST P2
U_MCU VDD - C_MCU_VDD1 P1
U_MCU PA3 - U_LTE TXD
J_PWR ~ - U_5V GND
U_MCU VBAT - C_MCU_VDDA P1
J_PWR ~ - U_5V GND
U_MCU VBAT - C_MCU_VDDA P1
J_PWR ~ - U_5V GND
U_5V TAB(VOUT) - U_3V3 VIN
U_MCU VDD - C_MCU_VDD1 P1
U_MCU PD1 - Y1 3
U_MCU PA14 - J_SWD 04
U_OPTO1 ~ - R_Q_BASE P1
J_PWR ~ - U_5V GND
U_5V TAB(VOUT) - U_3V3 VIN
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
J_PWR ~ - U_5V GND
U_LTE VBAT - U_LTE VBAT__1
R_FB1 P2 - R_FB2 P1
C_NRST P2 - R_BOOT0 P2
U_MCU VBAT - C_MCU_VDDA P1
U_MCU NRST - R_NRST P2
U_MCU PA9 - J_UART Pin_1
J_PWR ~ - U_5V GND
J_CT
R_FB1
Resistance
100kΩ
D_TVS
End of Life
C_MCU_VDD3
Capacitance
100nF
U_OPTO2
R_NRST
Resistance
10kΩ
R_STATUS
Resistance
1kΩ
R_BOOT0
Resistance
10kΩ
R_OPTO_LED2
Resistance
330Ω
C_3V3_OUT
Capacitance
22uF
C_LTE_BULK
Capacitance
100uF
C_RES
Capacitance
1000uF
J_VSENSE
U_OPTO1
C_NRST
Capacitance
100nF
C_4V_VCC
Capacitance
1uF
R_OPTO_LED
Resistance
330Ω
C_LTE_100N
Capacitance
100nF
R_Q_BASE
Resistance
4.7kΩ
J_RELAY_CONTACT
C_ACS_FILTER
Capacitance
1nF
C_MCU_VDD2
Capacitance
100nF
C_MCU_VDDA
Capacitance
100nF
C_MCU_VDD1
Capacitance
100nF
C_5V_OUT
Capacitance
22uF
C_4V_BOOT
Capacitance
100nF
R_FB2
Resistance
33.2kΩ
U_ACS
J_PWR
TP_RESET
Q1
J_SWD
L1
Inductance
8.2uH
Y1
K1
J_UART
J_ANT
D2
Manufacturer Part Number
1N4007
D_STATUS

Refine this doc
Ask about this doc
ERC Waivers — GLECS V4 Logic Controller
Status
Accepted, documented residual ERC warnings after first-pass schematic completion.
Summary
The schematic intentionally leaves five LTE/SIM auxiliary pins unpowered/unconnected. Flux ERC classifies them as power inputs, so they remain visible as Missing Power errors even though they are not required external power inputs for this design.
Accepted ERC Power Warnings

Table

ERC ItemDesign DecisionWhy AcceptedDo Not Fix By
J_SIM:VPPLeave unconnectedSIM VPP/programming voltage is unused on modern SIM cards; SIM1 power comes from U_LTE:USIM1_VDD to J_SIM:VCC.Do not tie to 3.3V/4V/5V.
U_LTE:VDD_1V8Leave unconnectedModule auxiliary/reference 1.8V rail; not used by the board-level STM32 interface. Main LTE power is on U_LTE VBAT pins 55/56/57.Do not back-feed external power.
U_LTE:VDD_2V8Leave unconnectedModule auxiliary/reference 2.8V rail; not required for the selected UART/SIM/RF interface.Do not back-feed external power.
U_LTE:VBUSLeave unconnectedUSB interface is not used in this design; LTE control is via UART2.Do not connect unless USB service port is intentionally added.
U_LTE:VBAT_ADCLeave unconnectedOptional LTE ADC battery-sense input is unused; board already powers LTE from regulated VCC_4V_LTE.Do not connect unless adding validated LTE voltage-sense divider.
Verified Main Connections
  • LTE main supply: VCC_4V_LTE to U_LTE VBAT pins 55, 56, 57 with C_LTE_BULK and C_LTE_100N.
  • LTE ground: all ground pads tied to GND_STAR.
  • LTE control/data: UART2, PWRKEY, RESET, STATUS connected to STM32.
  • SIM1: USIM1_VDD, DATA, CLK, RST, DET connected to J_SIM.
  • Antenna: U_LTE RF_ANT to J_ANT SIG; J_ANT grounds to GND_STAR.
Layout Reminder
During layout, keep LTE_RF_ANT short and controlled, preserve antenna keepout, and do not route relay/switching currents near the LTE/RF zone.

  • Status

  • Summary

  • Accepted ERC Power Warnings

  • Verified Main Connections

  • Layout Reminder

GLECS V4 Logic Controller thumbnail
STM32F103-based GLECS V4 pure logic controller with 12V input power tree, onboard 4G module, isolated relay control zone, sensors, OLED, debug headers, and 200x140mm two-layer PCB requirements.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$12.42–$14.12

Digi-Key

$16.88–$17.44

HQonline

$2.39–$2.84

LCSC

$12.63–$13.24

Mouser

$20.40–$595.82

TME

$5.41–$5.67

Verical

$8.97–$31.52

Controls