LED Blinker Circuit Design
Thought for 1 min 22 sec
Manufacturing files generated successfully:
- Gerber ZIP
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The DXF uses a
MILLING_CUTOUT layer and shows the 1.5mm non-plated full-height isolation slot centered at x=85mm on the 200×140mm board. Specify 2-layer FR4, ENIG in the fab order notes.Review package and DRC
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Board Bring-Up Plan — GLECS V4 Logic Controller
Prerequisites
- Equipment: current-limited 12V bench supply, DMM, oscilloscope, ST-Link/SWD programmer, USB-UART adapter, LTE SIM/antenna.
- Start with 12V current limit around 300mA, then raise only after rails are verified.
- Do not bridge GND_STAR and GND_RELAY; relay control crosses through U_OPTO1 only.
- Before interpreting ERC output, read the separate ERC waiver file for the accepted LTE/SIM auxiliary-pin warnings.
1. Visual Inspection
- Verify polarity/orientation: D_TVS, D2, electrolytic/bulk capacitors, U_MCU, U_LTE, J_SIM, J_ANT, K1, Q1, U_OPTO1.
- Confirm antenna connector and SIM holder soldering under magnification.
- Confirm relay contact terminal J_RELAY_CONTACT is isolated from logic ground.
2. Power Rail Verification
Table
| Rail | Source | Expected | Measure At | Current Limit / Pass Criteria |
|---|---|---|---|---|
| VCC_12V_INPUT | J_PWR | 12V | J_PWR / C_RES | No short to GND_STAR before power; within supply tolerance |
| VCC_5V | U_5V AMS1117-5.0 | 5.0V | C_5V_OUT P1 | ±5%; check AMS1117 heating because 12V→5V drop is high |
| VCC_3V3 | U_3V3 AMS1117-3.3 | 3.3V | C_3V3_OUT P1 | ±5%; MCU current should be modest |
| VCC_4V_LTE | U_4V LMR33630 | ~4.0V | C_LTE_BULK P1 | ±5%; verify ripple before installing/activating LTE |
| VCC_12V_RELAY | relay zone | 12V | K1 COIL1 / D2 cathode | Keep separate from GND_STAR except optocoupler path |
3. Critical Signals
Table
| Signal | Expected Idle | Probe At |
|---|---|---|
| MCU_NRST | High at 3.3V | TP_RESET / U_MCU NRST |
| MCU_BOOT0 | Low | R_BOOT0 / U_MCU BOOT0 |
| MCU_OSC_IN/OUT | 8MHz active after firmware config | Y1 pins |
| LTE_PWRKEY / LTE_RESET | Firmware controlled | U_LTE pins 1/16 |
| RELAY_CTRL | Low until commanded | R_OPTO_LED P1 |
4. Programming and Interfaces
- SWD: J_SWD = 3V3, SWDIO, GND, SWCLK, NRST.
- Debug UART: J_UART = UART1_TX_DEBUG, UART1_RX_DEBUG, GND.
- OLED: J_OLED = 3V3, GND, I2C1_SCL, I2C1_SDA.
- Sensors: J_DS18B20 and J_DHT22 use 3V3/GND/DATA with 4.7k pullups; U_ACS VOUT goes to ACS712_ADC.
5. Functional Validation
- Program STM32 over SWD and verify device ID.
- Blink D_STATUS via STATUS_LED.
- Scan OLED on I2C1.
- Read DS18B20, DHT22, and ACS712_ADC.
- Power LTE after confirming VCC_4V_LTE stability; test AT commands over UART2.
- Command RELAY_CTRL and verify K1 changes state while GND_STAR and GND_RELAY remain isolated.
Accepted ERC Notes
The remaining ERC Missing Power items are documented waivers, not unresolved supply wiring errors:
- J_SIM:VPP — unused SIM programming voltage pin.
- U_LTE:VDD_1V8 — unused/module auxiliary 1.8V pin.
- U_LTE:VDD_2V8 — unused/module auxiliary 2.8V pin.
- U_LTE:VBUS — USB not used; LTE is controlled over UART2.
- U_LTE:VBAT_ADC — optional LTE ADC sense input unused.
Main LTE power is VCC_4V_LTE into U_LTE VBAT pins 55/56/57, with local bulk and bypass capacitors populated.
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signals
4. Programming and Interfaces
5. Functional Validation
Accepted ERC Notes
