Part Information Review and Analysis
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Looking for "Digital I/O levels VIH VIL VOH VOL for IOVDD 1.8 V and 3.3 V" in PCM1861
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Here’s a complete execution of your 4 requested steps.
- Part information review
Part overview
Table
| Field | Value |
|---|---|
| MPN | PCM1861DBT |
| Manufacturer | Texas Instruments |
| Description | 110 dB 2-Channel Hardware-Controlled Audio ADC With Universal Front End |
| Package | 30-pin TSSOP (DBT) |
| Pin count | 30 |
| Designator prefix | IC |
| Mount | Hardware |
| Datasheet | Datasheet |
| Pricing/availability | Mouser: $5.41, stock ~3.2K (as shown in project context) |
Notes
- The schematic currently represents all 30 pins as Terminal components (one per pin) such as AVDD, DVDD, IOVDD, DOUT, BCK, LRCK, etc.
- Datasheet URL
- A datasheet URL is already set on this part: Datasheet. No update needed.
- Datasheet scan and metadata extraction
Key features
- High SNR performance: PCM1861/63/65: 110 dB; PCM1860/62/64: 103 dB
- ADC sample rate: 8 kHz to 192 kHz
- Up to four independent ADC channels available
- Single-ended 2.1 VRMS FS input; differential 4.2 VRMS FS input
- Hardware control (PCM1860/61)
- Single 3.3 V power-supply operation
- Integrated high-performance audio PLL; master or slave audio interface
- Power: < 85 mW (PCM1860/61/62/63) at 3.3 V
Recommended operating conditions
Table
| Parameter | Min | Nom | Max | Unit | Notes |
|---|---|---|---|---|---|
| AVDD | 3.0 | 3.3 | 3.6 | V | Analog supply to AGND |
| DVDD | 3.0 | 3.3 | 3.6 | V | Digital supply to DGND |
| IOVDD (option 1) | 1.62 | 1.8 | 1.98 | V | 1.8 V I/O option |
| IOVDD (option 2) | 3.0 | 3.3 | 3.6 | V | 3.3 V I/O option |
| LDO pin voltage | IOVDD − 0.3 | IOVDD | IOVDD + 0.3 | V | LDO pin is input when bypassing with external 1.8 V |
| TA | −40 | — | 125 | °C | Operating ambient temperature |
Electrical characteristics (selected)
Table
| Parameter | Condition | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| Full-scale input (SE) | 0 dB PGA | — | 2.1 | — | VRMS |
| Full-scale input (Diff) | 2.1 VRMS per pin | — | 4.2 | — | VRMS |
| SNR (SE) | 0 dB PGA, −60 dB input, master | — | 106 | — | dB |
| SNR (Diff) | 0 dB PGA, −60 dB input, master | — | 110 | — | dB |
| THD+N (Diff) | 0 dB PGA, −1 dB input, master | −93 | — | −85 | dB |
| THD+N (SE) | 0 dB PGA, −1 dB input, master | — | 87 | — | dB |
| PGA range | — | −12 | — | 32 | dB |
| Input impedance (per pin) | PCM1860/61/62/63 | — | 20 | — | kΩ |
| Energysense secondary ADC | Sampling rate | 8 | — | 192 | kHz |
MIC_BIAS (from datasheet)
Table
| Parameter | Typ |
|---|---|
| Mic bias voltage | 2.6 V |
| Mic bias current drive | 4 mA |
| Mic bias noise | 5 µVRMS |
Clocking (MCLK/SCKI and interface clocks)
Table
| Parameter | Condition | Min | Typ | Max |
|---|---|---|---|---|
| XTAL support | — | 15 | — | 35 MHz |
| MCLK frequency | 3.3 V on MCLK pin | 1 | — | 50 MHz |
| MCLK frequency | 1.8 V MCLK on XI pin | 1 | — | 50 MHz |
| MCLK duty cycle | 1.8 V MCLK | 48% | — | 52% |
| Max BCK | IOVDD = 3.3 V | — | — | 50 MHz |
| Max BCK | IOVDD = 1.8 V | — | — | 25 MHz |
ESD and thermal
Table
| Parameter | Value |
|---|---|
| ESD HBM | ±2000 V |
| ESD CDM | ±750 V |
| RθJA (DBT 30) | 79.6 °C/W |
| RθJC(top) | 15.1 °C/W |
| RθJB | 33.1 °C/W |
| ψJT | 0.4 °C/W |
| ψJB | 32.6 °C/W |
Pin configuration (DBT 30-pin TSSOP)
Table
| No. | Name | Type | Description |
|---|---|---|---|
| 1 | VINL2/VIN1M | Analog input | Analog input 2, L-channel (or differential M input for input 1) |
| 2 | VINR2/VIN2M | Analog input | Analog input 2, R-channel (or differential M input for input 2) |
| 3 | VINL1/VIN1P | Analog input | Analog input 1, L-channel (or differential P input for input 1) |
| 4 | VINR1/VIN2P | Analog input | Analog input 1, R-channel (or differential P input for input 2) |
| 5 | Mic Bias | Power | Microphone bias output |
| 6 | VREF | Power | Reference voltage output decoupling point (typically 0.5 AVDD). Connect 1 µF to AGND. |
| 7 | AGND | Power | Analog ground |
| 8 | AVDD | Power | Analog 3.3 V supply. Decouple 0.1 µF and 10 µF to AGND. |
| 9 | XO | Digital output | Crystal oscillator output |
| 10 | XI | Digital input | Crystal oscillator input or 1.8 V MCLK input |
| 11 | LDO | Power | Internal LDO decoupling output, or external 1.8 V input to bypass LDO. Decouple 0.1 µF and 10 µF to DGND. |
| 12 | DGND | Power | Digital ground |
| 13 | DVDD | Power | Digital 3.3 V supply. Decouple 0.1 µF and 10 µF to DGND. |
| 14 | IOVDD | Power | I/O supply (1.8 V or 3.3 V) |
| 15 | SCKI | Digital input | CMOS (3.3 V) master clock input |
| 16 | LRCK | Digital I/O | Audio word clock input/output |
| 17 | BCK | Digital I/O | Audio bit clock input/output |
| 18 | DOUT | Digital output | Audio data output |
| 19 | INT | Analog output | Interrupt for analog input detection (high = active, low = idle) |
| 20 | MD6 | Analog input | Analog MUX/gain select (with MD5, MD2); see table |
| 21 | MD5 | Analog input | Analog MUX/gain select |
| 22 | MD4 | Analog input | Audio format: high = left-justified, low = I2S |
| 23 | MD2 | Analog input | Analog MUX/gain select |
| 24 | MD3 | Digital input | Filter select: 0 = FIR, 1 = IIR low-latency |
| 25 | MD1 | Analog input | Audio interface mode (with MD0): 00 slave auto, 01 master 512×fS, 10 master 384×fS, 11 master 256×fS |
| 26 | MD0 | Analog input | Audio interface mode select (with MD1) |
| 27 | VINL4/VIN4M | Analog input | Analog input 4, L (or differential M for input 4) |
| 28 | VINR4/VIN3M | Analog input | Analog input 4, R (or differential M for input 3) |
| 29 | VINL3/VIN4P | Analog input | Analog input 3, L (or differential P for input 4) |
| 30 | VINR3/VIN3P | Analog input | Analog input 3, R (or differential P for input 3) |
Package/mechanical
- Package: DBT (TSSOP-30). Mechanical drawing: DBT0030A / R-PDSO-G30.
- Land pattern/dimensions should be taken from the linked package drawing. Numeric dimensions could not be machine-extracted here.
- Cross-check: symbol and footprint vs datasheet
Schematic symbol (pins)
- Pin count: 30 present in the symbol (30 Terminals). Matches the DBT package.
- Pin numbers and names match the datasheet mapping:
- VINL2/VIN1M is Pin 1 (matches datasheet).
- VINR3/VIN3P is Pin 30 (matches).
- SCKI is Pin 15; LRCK is Pin 16; BCK is Pin 17; DOUT is Pin 18 (all match).
- Supplies and grounds match numbering: AVDD=8, AGND=7, DVDD=13, DGND=12, IOVDD=14 (all match).
- Control pins MD0=26, MD1=25, MD2=23, MD3=24, MD4=22, MD5=21, MD6=20 (all match).
- Pin electrical types in the symbol are currently “Unspecified” for all pins. This won’t cause manufacturing errors, but it can reduce ERC effectiveness. Consider setting types to Power/Digital/Analog per the datasheet to improve checks.
Footprint
- One footprint present with 30 pads named to match all pin names. Pad naming aligns with schematic pin names and datasheet names.
- Mismatch risks to verify before manufacturing:
- Land pattern/pitch/alignment: The project data does not expose pad pitch, body size, or pad geometry for automated verification here. Ensure the footprint matches DBT (TSSOP-30) per mechanical drawing, including:
- Correct lead pitch (TSSOP-30), lead span, pad length/width, and courtyard.
- Pin 1 indicator location consistent with symbol pin 1 (VINL2/VIN1M).
- Footprint rotation/origin matching your assembly data.
- Solder mask and paste apertures: verify they follow TI recommendations for DBT to avoid solder bridging or insufficient solder.
- Land pattern/pitch/alignment: The project data does not expose pad pitch, body size, or pad geometry for automated verification here. Ensure the footprint matches DBT (TSSOP-30) per mechanical drawing, including:
- If you’d like, I can help measure pad pitch and compare to the TI drawing once you confirm the intended land pattern values for DBT or provide a 2D footprint detail export.
Open items
- Absolute Maximum Ratings: the PDF section did not machine-extract during this pass. If you want, I can pull exact limits by querying a direct PDF URL for the datasheet (not the GPN page) and extract 7.1 explicitly.
Would you like me to tighten pin electrical types in the symbol and verify footprint geometry against the DBT drawing in detail?
Run DRC/ERC checks
Verify footprint dimensions
Extract absolute max ratings
Fix pin electrical types
26 days
Ready.
Reviews
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Pricing & Availability
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Assets
PCM1861DBT-thumb.png
PCM1861DBT-thumbThumbnailkicad_mod
PCM1861DBT
SOP50P640X120-30N.kicad_modFootprintPCM1861DBT
PCM1861DBT.stp3D Model
PCM1861DBT
PCM1861DBT Symbol.svgDefaultControls
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