Part Datasheet and Footprint Verification
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Looking for "Absolute Maximum Ratings table" in esp32-s3_datasheet_en.pdf
Looking for "Recommended Operating Conditions" in esp32-s3_datasheet_en.pdf
Looking for "Electrical Characteristics" in esp32-s3_datasheet_en.pdf
Looking for "Current consumption" in esp32-s3_datasheet_en.pdf
Looking for "Power supply voltage" in esp32-s3_datasheet_en.pdf
Looking for "GPIO voltage levels thresholds VIH VIL VOH VOL" in esp32-s3_datasheet_en.pdf
Looking for "Wi-Fi features" in esp32-s3_datasheet_en.pdf
Looking for "Bluetooth Low Energy features" in esp32-s3_datasheet_en.pdf
Looking for "Package information mechanical dimensions" in esp32-s3_datasheet_en.pdf
Looking for "Package dimensions QFN" in esp32-s3_datasheet_en.pdf
Looking for "Pin description table" in esp32-s3_datasheet_en.pdf
Looking for "Pin definitions list of pins and functions" in esp32-s3_datasheet_en.pdf
Looking for "Pin count for ESP32-S3 packages" in esp32-s3_datasheet_en.pdf
Looking for "Naming ESP32-S3R16V variant meaning and embedded memory" in esp32-s3_datasheet_en.pdf
Looking for "SPI interface pins SPIQ SPID SPICLK SPIWP SPIHD VDD_SPI" in esp32-s3_datasheet_en.pdf
Looking for "Strapping pins list and default states" in esp32-s3_datasheet_en.pdf
Looking for "External crystal pins XTAL_P XTAL_N and 32K XTAL_32K_P XTAL_32K_N requirements" in esp32-s3_datasheet_en.pdf
Looking for "RF input LNA_IN pin and matching network guidelines" in esp32-s3_datasheet_en.pdf
Looking for "Thermal pad exposed pad connection recommendation" in esp32-s3_datasheet_en.pdf
Using PCB Layout Tool.
Here’s a complete execution of your 4 requested steps for the part project ESP32-S3R16V.
- Review of available part information in the project
- MPN: ESP32-S3R16V
- Manufacturer: Espressif
- Part type: Integrated Circuits
- Designator prefix: IC
- Datasheet property: Present — Datasheet
- Package: Not explicitly set in properties (symbol and footprint exist)
- Symbol pins present: 57 total (numbered 1..57), including LNA_IN (Pin 1), dual VDD3P3_1/VDD3P3_2 (Pins 2/3), CHIP_PU (Pin 4), and GND (Pin 57).
- Footprint: Present with pad names matching symbol pins (pads include LNA_IN, GPIOx, SPIx, VDDA_1/2, GND, etc.)
- Datasheet URL check and update
- Datasheet already set: Datasheet
- No change required.
- Datasheet scan — extracted metadata
Absolute Maximum Ratings
Table
| Parameter | Description | Min | Max | Unit |
|---|---|---|---|---|
| Input power pins | Allowed input voltage | –0.3 | 3.6 | V |
| Ioutput | Cumulative IO output current | — | 1500 | mA |
| TSTORE | Storage temperature | –40 | 150 | °C |
Recommended Operating Conditions
Table
| Parameter | Description | Min | Typ | Max | Unit | Notes |
|---|---|---|---|---|---|---|
| VDDA, VDD3P3 | Recommended input voltage | 3.0 | 3.3 | 3.6 | V | 1 |
| VDD3P3_RTC | Recommended input voltage | 3.0 | 3.3 | 3.6 | V | 2 |
| VDD_SPI (as input) | — | — | 1.8 / 3.3 | 3.6 | V | 2 |
| VDD3P3_CPU | Recommended input voltage | 3.0 | 3.3 | 3.6 | V | 3 |
| IVDD | Cumulative input current | 0.5 | — | — | A | 4 |
VDD_SPI Internal/Output Characteristics
Table
| Parameter | Description | Typ | Unit | Notes |
|---|---|---|---|---|
| RSPI | VDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM | 14 | Ω | 2 |
| ISPI | Output current when VDD_SPI powered by 1.8 V Flash Voltage Regulator | 40 | mA | — |
DC Characteristics (3.3 V, 25 °C)
Table
| Parameter | Description | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| CIN | Pin capacitance | — | 2 | — | pF |
| VIH | High-level input voltage | 0.75 × VDD | — | VDD + 0.3 | V |
| VIL | Low-level input voltage | –0.3 | — | 0.25 × VDD | V |
| VIL_nRST | CHIP_PU reset voltage | –0.3 | — | 0.25 × VDD | V |
ADC Characteristics
Table
| Parameter | Description | Min | Max | Unit |
|---|---|---|---|---|
| DNL | Differential nonlinearity | –4 | 4 | LSB |
| INL | Integral nonlinearity | –8 | 8 | LSB |
| Sampling rate | — | — | 100 kSPS | — |
Current Consumption (3.3 V, 25 °C, peaks/typicals per tables)
Table
| Mode | Condition | Value |
|---|---|---|
| Wi‑Fi TX | 802.11b, 1 Mbps, @21 dBm | 340 mA (peak) |
| Wi‑Fi TX | 802.11g, 54 Mbps, @19 dBm | 291 mA (peak) |
| Wi‑Fi TX | 802.11n, HT20, MCS7, @18.5 dBm | 283 mA (peak) |
| Wi‑Fi TX | 802.11n, HT40, MCS7, @18 dBm | 286 mA (peak) |
| Wi‑Fi RX | 802.11b/g/n, HT20 | 88 mA (peak) |
| Wi‑Fi RX | 802.11n, HT40 | 91 mA (peak) |
| BLE TX | @ 21.0 dBm | 335 mA (peak) |
| BLE TX | @ 9.0 dBm | 193 mA (peak) |
| BLE TX | @ 0 dBm | 176 mA (peak) |
| BLE TX | @ –15.0 dBm | 116 mA (peak) |
| BLE RX | — | 93 mA (peak) |
| Light‑sleep | VDD_SPI/Wi‑Fi off, GPIOs Hi‑Z | 240 µA (typ) |
| Deep‑sleep | RTC mem + peripherals on | 8 µA (typ) |
| Deep‑sleep | RTC mem on, peripherals off | 7 µA (typ) |
| Power off | CHIP_PU low | 1 µA (typ) |
Pin Overview (per Table 2-1)
Table
| Range | Notable pins in range |
|---|---|
| 1–4 | LNA_IN(1), VDD3P3(2,3), CHIP_PU(4) |
| 5–18 | GPIO0..GPIO13 |
| 19–27 | GPIO14, VDD3P3_RTC(20), XTAL_32K_P/N(21/22), GPIO17..GPIO21 |
| 28–37 | SPICS1(28), VDD_SPI(29), SPIHD/WP/CS0/CLK/Q/D(30–35), SPICLK_N/P(36/37) |
| 38–46 | GPIO33..GPIO38, MTCK(44), MTDO(45), VDD3P3_CPU(46) |
| 47–52 | MTDI(47), MTMS(48), U0TXD(49), U0RXD(50), GPIO45(51), GPIO46(52) |
| 53–57 | XTAL_N(53), XTAL_P(54), VDDA(55,56), GND(57, exposed pad) |
Strapping Pins (default states)
Table
| Pin | Default |
|---|---|
| GPIO0 | Weak pull‑up (1) |
| GPIO3 | Floating |
| GPIO45 | Weak pull‑down (0) |
| GPIO46 | Weak pull‑down (0) |
Variant details (Table 1-1)
Table
| Part | In‑package Flash | In‑package PSRAM | Ambient temp | VDD_SPI | Chip rev |
|---|---|---|---|---|---|
| ESP32‑S3R16V | — | 16 MB (Octal SPI) | –40 ∼ 65 °C | 1.8 V | v0.2 |
Wi‑Fi / Bluetooth LE features
- Wi‑Fi: 802.11b/g/n; HT20/HT40; MCS0‑7; data rate up to 150 Mbps; RX STBC; adjustable TX power; antenna diversity with external RF switch.
- Bluetooth LE: Bluetooth 5 + Mesh; PHYs: 1M, 2M, Coded (125/500 kbps); Class 1 TX power; LE Advertising Extensions; multiple sets; simultaneous advertising and scanning.
Package and mechanical
- Package: QFN56 (7×7 mm), exposed ground pad present (datasheet Figure 7‑1).
- Thermal pad guidance: connect EPAD to ground with at least nine ground vias; use paste windowing as recommended.
RF/LNA_IN guidance
- 50 Ω controlled‑impedance RF trace, CLC matching near the chip; use 0201 parts; stub on first capacitor to suppress harmonics; include antenna ESD.
Crystals
- Main crystal: 40 MHz only; include ~24 nH series element on XTAL_P initially; tune C1/C4 per CL formula.
- 32.768 kHz RTC crystal optional; ESR ≤ 70 kΩ; bias resistor 5 MΩ < R ≤ 10 MΩ if needed.
- Cross‑check: symbol and footprint vs datasheet
Symbol integrity
- Pin count: Symbol contains 57 pins (1..57) including the exposed pad GND as Pin 57 — matches QFN56 + EPAD in the datasheet.
- Naming and numbering: Spot‑checks align with Table 2‑1 — e.g., LNA_IN = Pin 1, VDD3P3_1 = Pin 2, CHIP_PU = Pin 4, VDD_SPI = Pin 29, SPI bus pins (30–35), SPICLK_N/P (36/37), VDD3P3_CPU = Pin 46, U0TXD/U0RXD = Pins 49/50, VDDA_1/VDDA_2 = Pins 55/56, GND = Pin 57.
- Result: No symbol mismatches found.
Footprint integrity
- Pad coverage: Footprint includes pads named for all symbol pins, including an EPAD labeled GND — consistent with datasheet requirement for an exposed ground pad.
- Mechanical dimensions: The footprint data exposed to the tool does not include pad pitch/size or body size; thus, I cannot verify QFN56 7×7 mm outline, pin‑1 orientation marker, or pad pitch against the datasheet drawing.
- Thermal viaing: Datasheet calls for “at least nine” ground vias in the EPAD; via stitching cannot be verified from the available footprint metadata.
Flags and recommendations
- Missing/uncertain: Package properties are not explicitly set in the part metadata; consider setting “QFN56, 7×7 mm” to avoid ordering ambiguity.
- Verification needed: Manually confirm in the Footprint editor that:
- Body size is 7×7 mm and matches the ESP32‑S3 QFN56 land pattern.
- Pin pitch and pad dimensions match the datasheet’s QFN56 drawing.
- Pin‑1 marker and pad numbering around the perimeter follow the datasheet orientation.
- EPAD solder paste windowing and via‑in‑pad/thermal vias follow the recommendations (≥ 9 vias tied to GND).
- Electrical variant note: For ESP32‑S3R16V, VDD_SPI domain is 1.8 V (per Table 1‑1). Ensure any reference designs and net annotations reflect 1.8 V for in‑package PSRAM/flash operation.
If you want, I can proceed to add the missing package property and prepare a short checklist for verifying the footprint dimensions against the datasheet land pattern.
Run ERC/DRC checks
Verify pin-1 orientation
Add package metadata
Check RF matching guidance
20 days
Ready.
Reviews
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Assets
ESP32-S3R16V-thumb.png
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ESP32-S3R16V
ESP32-S3R16V Symbol.svgDefaultESP32-S3R16V
ESP32-S3R16V.stp3D Modelkicad_mod
ESP32-S3R16V
QFN40P700X700X90-57N-D.kicad_modFootprintControls
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