Pixel 7 Car Power Mod
Thought for 10 sec
I’ll retry the complete datasheet and circuit audit now, covering every active device, the full power path, fault cases, thermal limits, and the 46 × 80 × 5 mm envelope. I’ll save the detailed pass/fail report in the project files and make no circuit changes unless a separate correction step is warranted.
Worked for 6 mins 33 sec
Created a project doc
Full Datasheet and Circuit Validation
Project: Pixel 7 USB-C Battery Emulator Validation type: Read-only schematic/BOM/connectivity/datasheet review
Full datasheet and circuit validation completed. Current verdict: FAIL—do not connect this revision to the phone yet. The main blockers are the undersized LM5176 current shunt, inadequately driven Q8, unverified charge-back protection, provisional compensation/capacitors, and oversized PCB.
Detailed calculations, component-by-component results, citations, and corrections are in Full Datasheet and Circuit Validation.
Suggested next steps
- Correct the safety/blocker findings.
- Revalidate the revised power stage and fault protection.
- Then redesign the PCB for the 46 × 80 × 5 mm envelope.
Fix and revalidate
Fix blocker findings
Find better parts
Review capacitor choices
Update protection logic
Prepare compact layout
Refine this doc
Ask about this doc
Power and Design Notes
1. Power-path recalculation
Target output is 4.15 V × 5 A = 20.75 W. Required input is 23.1 W at 90% efficiency. Worst-case calculations use the minimum 4.5 V input.
The protection limit is intentionally contract-conservative: TPS26630 RILIM=6.49 kΩ gives
IOL=18/RILIM=2.77 A nominal. Datasheet spread is approximately ±8%, so the high limit is about 2.995 A. This setting does not exceed a 3 A USB-C ceiling.- 4.5 V, 2.77 A, 88%: 10.97 W output, 2.64 A at 4.15 V.
- 5 V, 2.77 A, 88%: 12.19 W output, 2.94 A at 4.15 V.
- 5 V/3 A source maximum, 88%: 13.2 W output, 3.18 A at 4.15 V. This is the theoretical contract ceiling, not 5 A output.
- 9 V, 2.77 A, 92%: 22.94 W output, enough for the 20.75 W/5 A target if the negotiated PDO allows at least about 2.51 A.
- 15/20 V contracts have ample voltage-power headroom at this board limit, but the actual negotiated current remains authoritative.
No contract telemetry: the board only taps VBUS/GND and cannot read CC or PD messages. A fixed 2.77 A limit is defensible against a 3 A ceiling but can still exceed a lower-current negotiated PDO. The phone and source must negotiate and enforce the contract; source collapse/retry is possible on low-current PDOs. A minimum 30 W PD/PPS adapter is recommended.
2. Why the original protection was replaced
The prior SMBJ22A had 22 V standoff but clamped to 35.5 V at 17.7 A (10/1000 µs), above the TPS259830's 30 V absolute maximum. The original BSC010N04LS6 blocking FET was only 40 V. The prior 5.5 A current limit could also demand more than a valid 5 V/3 A contract and did not solve contract awareness.
3. Coordinated protection solution
D1 SMBJ24A
- 24 V working standoff: safe for 21 V continuous VBUS.
- 26.7–29.5 V breakdown.
- 38.9 V maximum clamp at 16 A for the datasheet pulse condition.
- Selected so normal 21 V operation does not enter breakdown and the rated clamp remains below downstream 60 V ratings.
U1 TPS26630RGE
- Recommended input 4.5–60 V; 67 V absolute maximum (75 V, 10 ms transient at 25°C).
- 31 mΩ-class integrated path, 0.6–6 A adjustable limit.
- TPS26630 uses 1× active current limiting; it does not intentionally pass the 2× pulse-current mode of TPS26631/33/35/37.
- R1=6.49 kΩ: 2.77 A nominal, about 2.995 A high-tolerance limit.
- R2=715 kΩ, R3=210 kΩ, R4=49.9 kΩ: about 4.50 V UVLO and 23.45 V OVP nominal using the 1.2 V thresholds.
- C2=10 nF on dVdT; MODE grounded for auto-retry.
- Internal SHDN bias is used; IMON/FLT/PGOOD are intentionally unused; PGTH is grounded.
Reverse blocking
- Q1 CSD19537Q3T: 100 V NFET used as the external source-to-IN blocking device recommended in the TPS2663x application guidance.
- Q6 BSS138: DRV-controlled fast gate pulldown required by the datasheet.
- This gives true reverse-current comparator action rather than waiting only for UVLO after VBUS collapse.
Downstream coordination
- LM5176: 60 V absolute maximum on VIN and switch nodes.
- Q2–Q5 AONS66614: 60 V VDS, 2.9 mΩ max at 10 V and 4.1 mΩ max at 4.5 V.
- Q1: 100 V VDS.
- A 38.9 V rated TVS clamp is therefore compatible with the revised eFuse and blocking FET and has about 21 V nominal margin to the 60 V converter/bridge ratings. This margin must absorb tolerance, temperature, wiring inductance, and PCB overshoot; oscilloscope validation remains mandatory.
4. Converter/power-stage review retained
- LM5176 recommended VIN 4.2–55 V, 60 V absolute.
- 12 mΩ shunt gives nominal 6.7 A buck valley and 10 A boost peak thresholds; minimum thresholds are lower (66 mV buck, 100 mV boost) and must be included in final load validation.
- XAL7030-222MEC: 2.2 µH ±20%, 15.07 mΩ max DCR, 18 A typical saturation, 12.9 A at 40°C rise, about 3.1 mm high.
- AONS66614 bridge FETs are 60 V parts; low-voltage gate enhancement is documented at 4.5 V.
- Existing 35 V input MLCCs remain adequate for 21 V continuous but exact DC-bias effective capacitance must be verified.
- Existing 10 V output ceramics are adequate at 4.15 V; effective capacitance after bias must remain at least 80 µF target.
5. Unresolved passive/loop items
- R11/C14/C15 compensation is still provisional and must be recalculated with final effective COUT and ESR using TI's model, then verified by Bode and load-step testing.
- C22–C25 330 µF polymer entries remain placeholders. Exact MPN, ESR, ripple current, leakage, footprint, availability, and ≤5 mm installed height are unresolved.
- Buffering cannot replace source power:
C=I·dt/dV; a 3 A deficit for 100 µs at 200 mV needs 1.5 mF, and for 1 ms needs 15 mF.
6. Required bench validation
- Current-limited startup at 4.5 V and 5 V.
- Line sweep at 4.5/5/9/15/20/21 V at light load and source-limited load.
- Confirm RILIM limit distribution and that the source contract is not violated.
- Capture VBUS_TAP, EFUSE_IN, VIN_PROTECTED, LM5176 SW1/SW2, and BMS_CELL_PLUS during hot-plug, PD transition, overload, short, and disconnect.
- Confirm D1 clamp and all overshoot remain below U1/LM5176/MOSFET absolute maxima.
- Verify fast reverse-current blocking and no sustained VBUS backfeed.
- Perform Bode/load-step testing with final output capacitor MPNs.
- Thermal soak at 5 A output only with a verified higher-voltage PD contract and within the 46 × 80 × 5 mm installation.
- Validate Pixel/BMS authentication, SOC, thermistor, and protection behavior without a cell.
7. BMS-side charge-back protection revision
The LM5176 output bank is now
CONVERTER_4V15; the original BMS Cell+ pad remains BMS_CELL_PLUS. U3 LTC4359 and Q7 DMN3008SFG form the boundary. Q7 source is on the converter side and drain is on the BMS side, so its intrinsic body diode conducts only converter-to-BMS during startup from zero. U3 then enhances Q7 and regulates about 30 mV forward drop, while a detected reverse current pulls GATE to SOURCE in approximately 0.3 us. The BMS therefore cannot force charge current into the LM5176/output capacitor bank in normal operation.At 5 A, Q7's 5.5 mOhm maximum RDS(on) at VGS=4.5 V gives about 27.5 mV drop and 0.138 W dissipation, practical with the specified PowerDI3333-8 copper. Q7 is 30 V VDS and +/-20 V VGS; U3 is rated 4-80 V and has internal gate limiting compatible with 4.5 V logic MOSFETs. U3 SHDN is tied to the converter rail so it starts whenever the 4.15 V source is present. The body diode supplies initial BMS-side voltage before the gate charge pump is active.
U4 TLV3012, R14=261 kOhm 0.1%, and R15=100 kOhm 0.1% monitor the BMS node against U4's 1.242 V reference. Nominal trip is about 4.48 V. Allowing the original TLV3012 reference limits (1.208-1.276 V), divider tolerance, and comparator offset gives an estimated trip band roughly 4.3-4.65 V: above the 4.15 V regulated operating band and around the high-voltage phone-cell charge region, but below the 6.3 V upstream polymer rating and the 10 V local C27 rating. This tolerance band must be measured on prototypes.
When BMS_CELL_PLUS exceeds the threshold, U4's push-pull output turns on Q8 AONS66614. Ten 22 Ohm, 1 W, 2512 resistors in parallel form a 2.2 Ohm switched dump. It is not a permanent load: below threshold Q8 is off and R16 holds its gate low. Near 4.48 V the bank can absorb about 2.0 A and about 9.1 W total (approximately 0.91 W per resistor), intended only for short attempted-charge events. Sustained phone charge current, duty cycle, and BMS behavior are unknown and must not be assumed. If measured current exceeds about 2 A or persists thermally, firmware/phone behavior cannot save this passive circuit; testing must stop and the dump energy handling must be redesigned.
Forward-power state: LM5176 regulates CONVERTER_4V15, Q7 body diode starts the BMS node, U3 enhances Q7, Q8 remains off, and TP3 receives the low-loss 4.15 V rail. Attempted-charge-back state: U3 rapidly turns Q7 off so reverse current cannot reach LM5176 or its bulk capacitors; the BMS node rises only to the comparator band before Q8 connects the pulse dump bank. C27 is a 10 uF/10 V local capacitor after the blocker and C26/C28 support the comparator/reference.
Bench validation additions: force reverse current into TP3 with the converter energized and unenergized; capture BMS_CELL_PLUS, CONVERTER_4V15, IDEAL_GATE, and DUMP_GATE; verify no measurable reverse charge reaches C16-C25 or Q4; characterize trip/reset chatter, peak dump current, resistor temperature, and maximum safe pulse duration. Do not perform sustained reverse-current tests until a measured Pixel/BMS charge-current profile is available.
1. Power-path recalculation
2. Why the original protection was replaced
3. Coordinated protection solution
D1 SMBJ24A
U1 TPS26630RGE
Reverse blocking
Downstream coordination
4. Converter/power-stage review retained
5. Unresolved passive/loop items
6. Required bench validation
7. BMS-side charge-back protection revision
