I’ll identify every failed or marginal component from the latest validation, evaluate stronger drop-in or topology-compatible alternatives for sustained and transient output current, then implement the best practical corrections and revalidate the complete power path.
I prepared the full upgrade scope and constraints, but execution is blocked because no ACUs are currently available. No schematic changes were made.
Remaining work:
Recalculate the 15 V input power budget for 6 A continuous / 8 A transient output.
Identify and replace failed or marginal parts, especially the input protection, switching MOSFETs, shunt, inductor, capacitors, and reverse-blocking path.
Verify losses, temperature, package height, and hand-solderability.
Restore/confirm connectivity after replacements.
Rerun ERC and power-stage validation.
Update the validation report with the final pass/fail verdict.
No changes could be made because ACUs are currently unavailable.
The revised validation should include 20 V PD input as the preferred option: it reduces cable and input current, but requires rechecking 20 V hot-plug margin, capacitor/eFuse/MOSFET ratings, duty cycle, switching losses, and PD-trigger behavior. Remaining work is to select stronger current-path components, replace failed/marginal parts, restore connectivity, and rerun ERC plus thermal/power-stage validation.
Project: Pixel 7 USB-C Battery Emulator Validation type: Read-only schematic/BOM/connectivity/datasheet review Scope date: 2026-07-30; fresh final-architecture review appended 2026-08-06 Assumptions applied: nominal 15 V automotive USB-PD source/trigger; 4.15 V output into separated Pixel 7 battery BMS/flex cell terminals; 6 A continuous and 8 A transient targets; no lithium cell; native-USB charger connection must be non-destructive; all PCB components top-side; bottom mostly solid GND thermally coupled through an insulating pad to phone backplate; maximum 46 × 80 × 5 mm.
1. Executive verdict
Overall: FAIL — not safe to prototype in a phone or connect to the Pixel/native charger as presently drawn. A current-limited, isolated bench breadboard/PCB experiment may be possible only after the blocker items below are corrected and independently re-reviewed.
The schematic has a recognizable and mostly coherent power architecture, but it does not credibly guarantee 6 A continuous or 8 A transient output, does not prove non-destructive behavior during native-USB charging, and the present PCB does not fit the required envelope. The principal electrical blocker is the 12 mΩ LM5176 cycle-current shunt: the HTSSOP buck valley threshold is 66/80/94 mV, corresponding to only 5.5/6.67/7.83 A before ripple and tolerance. At 15 V-to-4.15 V buck operation, 6 A is not guaranteed and 8 A is outside the maximum threshold. The independent dump switch Q8 is also not guaranteed to turn on because NCE6080K has RDS(on) specified only at 10 V and VGS(th) up to 4 V, while TLV3012 can drive it only from the approximately 4.3–4.6 V BMS rail.
Priority blockers
SAFETY/BLOCKER — native-USB charge handling is unqualified. The clamp bank is approximately 2.2 Ω and absorbs only about 2.0 A at 4.48 V (~9.1 W total, ~0.91 W per 1 W resistor). It has no defined pulse-duration/thermal limit, no sustained-current capability, and no evidence that Pixel charge-back current is ≤2 A. Accidental charger connection therefore cannot be called non-destructive.
BLOCKER — Q8 gate-drive incompatibility. NCE6080K is a standard 10 V-characterized MOSFET; no RDS(on) guarantee exists at the actual ~4.5 V gate drive. Replace it with a logic-level MOSFET having guaranteed RDS(on) at 4.5 V (and adequate SOA), or add a suitable gate driver/supply.
BLOCKER — 6 A/8 A current target not supported by current limit. R6=12 mΩ yields 5.5 A minimum buck valley limit and 7.83 A maximum; ripple reduces available DC output. Recalculate the sense resistor and slope compensation for guaranteed 6 A continuous plus 8 A transient, while checking inductor/FET peak current and short-circuit energy.
BLOCKER — compensation and output capacitors are placeholders. R11/C14/C15 are explicitly provisional; C22–C25 have no exact MPN, ESR, ripple rating, leakage, DC-bias data, or verified height. Stability and transient response cannot be approved.
BLOCKER — mechanical design fails. Current board is 160 × 100 mm and component bounding box is 104.75 × 100.79 mm, versus 46 × 80 mm maximum. All 71 parts are top-side, but fit, routing, copper area, and thermal path have not been demonstrated in the target envelope.
HIGH — project documentation is stale versus the actual BOM. Existing files name Q1 as CSD19537Q3T, Q7 as DMN3008SFG, and Q8 as AONS66614; actual schematic/BOM uses NCEP0178AK, AOD508, and NCE6080K. This report validates the actual drawn parts.
HIGH — no PD trigger/controller or contract telemetry exists on this schematic. TP1/TP2 are direct VBUS/GND pads. A separate trigger/phone assembly must establish 15 V before significant load; the board cannot distinguish a 5 V default/negotiation state or a lower-current PDO.
2. Inspected design state
71 schematic components, 36 named nets.
Active power chain: TP1/VBUS_TAP → Q1 + U1/Q6 reverse-blocking eFuse front end → VIN_PROTECTED → LM5176 four-switch bridge Q2–Q5 + L1 → CONVERTER_4V15 → LTC4359/Q7 → BMS_CELL_PLUS/TP3.
BMS-side clamp: TLV3012 + R14/R15 → Q8 → ten parallel 22 Ω/1 W resistors.
TP2 and TP4 share GND.
PCB: four copper layers; all components top-side; one fill; 51 vias; 141 unrouted airwires. The airwires are expected for an unfinished PCB and are not schematic-connectivity errors, but the PCB is not manufacturing-ready.
ERC/design-review query returned no listed schematic ERC violations in the requested ERC categories. Logical net membership is complete for the named nets inspected. This does not validate analog behavior or PCB routing.
3. Power budget and limits at 15 V
Table
Condition
Output power
Input current @90%
Input current @85%
Assessment
4.15 V, 6 A continuous
24.9 W
1.84 A
1.95 A
Fits a 15 V/3 A (45 W) contract and U1's 2.77 A nominal limit, but converter current/thermal margins are unproven.
4.15 V, 8 A transient
33.2 W
2.46 A
2.60 A
Below 2.77 A nominal only at nominal 15 V and assumed efficiency; close to source/eFuse limits under droop and losses. Converter cycle limit fails.
A credible 15 V source should provide at least 45 W / 3 A. A 15 V/2 A PDO is insufficient for the 8 A target and marginal after losses for 6 A. The board cannot read the contract.
First-order losses
R6 sense shunt: 0.432 W at 6 A; 0.768 W at 8 A. This is within its nominal 2 W rating but is a concentrated heat source and changes resistance with temperature.
Q7 AOD508 using 4.5 mΩ max at VGS=4.5 V: 0.162 W at 6 A and 0.288 W at 8 A, before hot RDS(on) increase.
Each actively conducting AONS66614 at 4.1 mΩ max (4.5 V drive) dissipates ~0.148 W at 6 A and ~0.262 W at 8 A; at ~7 V gate drive use 10 V data only as an optimistic bound. Switching, dead-time/body-diode, gate-drive, inductor, copper, eFuse, and capacitor ESR losses remain additional. A total converter/system loss of roughly 2.8–4.9 W corresponds to 90–85% at 24.9–33.2 W output and must be removed from a sealed 5 mm cavity.
U1 integrated path at approximately 31 mΩ would dissipate ~0.11 W at 1.84 A and ~0.19 W at 2.46 A, excluding transient current-limit heating.
L1 DCR max 15.07 mΩ gives ~0.54 W at 6 A and ~0.96 W at 8 A before AC core/copper loss.
Capacitor energy/transient support
Nominal drawn output capacitance is four 330 µF polymers plus six 22 µF ceramics = 1452 µF. Nominal stored energy at 4.15 V is only about 12.5 mJ. Ignoring ESR and bias, a 2 A deficit causing 0.2 V droop lasts about 145 µs. Effective ceramic capacitance is lower under DC bias; polymer ESR produces an immediate step. This bank cannot sustain millisecond-scale 8 A bursts unless the converter/source delivers nearly all of the power. Exact MPNs are mandatory.
4. Functional-block audit
4.1 PD-trigger handoff and 5 V negotiation — CONDITIONAL / HIGH
The board contains no CC pins, PD controller, or trigger IC. TP1 directly follows the phone/trigger VBUS. U1 and U2 both have about 4.5 V turn-on thresholds, so they may begin loading during the 5 V default/negotiation phase. U1 limits at 2.77 A nominal, but that can still exceed a default-current or lower-current PDO. A separate verified trigger must negotiate 15 V before enabling this board, or an explicit delayed/contract-qualified enable must be added. Verify hot-plug and PD renegotiation with oscilloscope and programmable PD source.
4.2 Input TVS/eFuse/UVLO/OVP/inrush — CONDITIONAL / HIGH
D1 SMBJ24A: PASS for 21 V steady-state standoff; 24 V VRWM, 26.7–29.5 V breakdown, 38.9 V clamp at 16 A on the specified 10/1000 µs pulse. It is not proof against arbitrary automotive surge energy or cable inductance overshoot.
U1 TPS26630RGE: pin map matches the 24-pin RGE VQFN plus exposed GND pad. Recommended 4.5–60 V; 67 V abs max (75 V/10 ms at 25°C); -40 to 125°C operation. R1=6.49 kΩ gives 2.77 A nominal by IOL=18/RILIM. R2/R3/R4 implement the intended UVLO/OVP ladder. C1=100 nF and C2=10 nF meet minimum local/dVdT capacitance. Exposed pad must be soldered with thermal vias.
Q1 orientation is correct per TPS2663 guidance: source to IN_SYS/VBUS_TAP, drain to U1 IN, gate to B_GATE. Q6 is correctly used as DRV-controlled fast pull-down.
Cable inductance, input capacitance and dV/dt/inrush waveforms are not quantified. U1 active-limit SOA/thermal stress during repeated auto-retry or a short remains unverified.
Corrective action: define the automotive source surge standard and wiring inductance; calculate hot-plug energy and eFuse fault timer behavior; bench-test at temperature; add/verify local damping and a source-qualified fuse if required.
The LM5176PWPR symbol pin numbers match TI's HTSSOP-28 PWP mapping, including EP. VIN/VISNS, VOSNS, AGND/PGND/EP, VCC, BOOT/SW, gate outputs, FB, RT, SS and COMP are connected consistently with the topology. BIAS and PGOOD are left unconnected; that is permissible. DITH is grounded. ISNS+ and ISNS− are shorted to disable average-current limiting. EP is grounded as required.
Input range: 4.2–55 V recommended, 60 V abs max; 15 V nominal passes. 38.9 V rated TVS clamp leaves ~21 V nominal margin, but switching/trace overshoot must remain below 60 V.
Frequency: R9=27.4 kΩ is intended for 300 kHz — CONDITIONAL pending equation/table confirmation across tolerance.
Gate drive: VCC regulates ~6.95–7.88 V at adequate VIN; AONS66614 is fully compatible and has 4.5 V/10 V RDS(on) characterization. At low 4.5–5 V VIN, VCC tracks VIN and the 4.5 V RDS(on) limit applies.
Bootstrap: 100 nF BOOT-to-SW and BAT54H charging diodes are topologically correct. BAT54H is 30 V/200 mA; reverse stress is mainly VCC-referenced, but switching overshoot must be measured.
Current limit: FAIL for requested load. R6=12 mΩ produces 5.5/6.67/7.83 A buck valley thresholds from 66/80/94 mV. Six amperes is not guaranteed after ripple; 8 A exceeds even the maximum threshold. Boost peak threshold is 8.33/10/11.67 A, but nominal 15 V operation is buck mode.
Compensation: R11=10 kΩ, C14=33 nF and C15=560 pF are explicitly provisional. No plant model/Bode analysis exists for the final 2.2 µH and actual COUT/ESR. FAIL until verified.
Soft start: C12=100 nF is plausible but must be checked against final inrush and BMS startup requirements.
Corrective action: redesign R6 and C13 together for guaranteed load and short-circuit protection; run TI LM5176 design calculator/model with exact FET, inductor and capacitor data; verify loop gain, line/load transient and startup at 5/9/15/21 V.
4.4 Four AONS66614 bridge MOSFETs Q2–Q5 — CONDITIONAL / HIGH
Exact part: AONS66614, DFN5×6, 60 V, ±20 V VGS, -55 to 150°C, 2.9 mΩ max at 10 V and 4.1 mΩ max at 4.5 V, Qg max 75 nC at 10 V / 38 nC at 4.5 V. Symbol has pins 1–3 sources, 4 gate, 5–8 drain plus duplicated drain pad representation; logical mapping and half-bridge orientation are consistent. Package is low-profile but bottom-pad/DFN and not hand-solder-friendly. The 60 V rating has limited overshoot margin. SOA curves are single-pulse/heatsink dependent; 6/8 A switching must be validated thermally with real copper.
4.5 Inductor L1 — CONDITIONAL / HIGH
XAL7030-222MEC: 2.2 µH ±20%, DCR 15.07 mΩ max, 18 A typical saturation (30% L drop), 10 A for 20°C rise and 12.9 A for 40°C rise, -40 to 125°C ambient with derating, 7.5×7.5 mm, 3.1 mm max height. It fits the 5 mm component-height limit by itself, but at 8 A plus ripple its hot-cavity loss and core temperature require measurement. It is a bottom-terminated molded part, not side-leaded/hand-solder preferred.
4.6 Input/output capacitors — FAIL / BLOCKER
C5–C8 are generic 10 µF/35 V 1210 MLCCs with no exact MPN; effective capacitance at 15–21 V, ripple current and anti-ferroelectric behavior cannot be verified. C16–C21 are generic 22 µF/10 V 1210 MLCCs with no MPN/DC-bias curve. C22–C25 are generic 330 µF/6.3 V placeholders; exact polymer type, ESR, ripple, leakage, tolerance, lifetime, polarity, footprint and height are unknown. A generic Non-Polarized Capacitor property is especially inadequate for likely polarized polymer parts. Assign exact MPNs and repeat stability, ripple, thermal, stored-energy and height checks.
4.7 LTC4359/Q7 ideal diode and reverse blocking — CONDITIONAL / HIGH
U3 is exact LTC4359HS8#PBF, SO-8, -40 to 125°C; symbol pins match GATE1, SOURCE2, NC3, IN4, SHDN5, VSS6, NC7, OUT8. It operates from 4–80 V, regulates ~30 mV forward drop, and turns off in 0.3–0.5 µs. SHDN tied to IN is recommended. IN/SOURCE/Q7 source are on CONVERTER_4V15 and OUT/Q7 drain on BMS_CELL_PLUS, so the body diode and controlled direction are converter-to-BMS — correct.
Q7 AOD508 is 30 V, ±20 V VGS, RDS(on) max 4.5 mΩ at 4.5 V, Qg max 23 nC at 4.5 V, -55 to 175°C, DPAK. It is compatible with LTC4359's low-voltage gate drive and has ample VDS margin for a 4–5 V node. DPAK is side-leaded and ~2.3 mm high, reasonably hand-solderable with a large drain tab.
Limitations: LTC4359 does not interrupt its MOSFET body-diode forward path in shutdown; only reverse current is blocked. Its minimum operating voltage is 4 V, so startup below 4 V relies on the correctly oriented body diode. Native-USB safety still depends on the downstream dump circuit and actual BMS behavior.
U4 exact variant TLV3012AIDBVT is push-pull, SOT-23-6, -40 to 125°C, 1.8–5.5 V recommended, 7 V abs max, 2.8 µA typical IQ, 1.208–1.276 V reference, up to 15 mV input offset. Pin mapping is correct. It is powered from BMS_CELL_PLUS; operation below 1.8 V is undefined during startup, but R16 holds Q8 gate low.
Nominal threshold is 1.242 × (261k+100k)/100k = 4.484 V. Worst-case reference alone gives 4.362–4.606 V; adding 0.1% divider tolerance, offset and temperature widens this. There is no external positive-feedback resistor; the non-B TLV3012 data does not guarantee the 2–8 mV built-in hysteresis listed for B variants. Chatter and dump heating near threshold are therefore unresolved.
Q8 NCE6080K is not gate-drive compatible by guarantee: VGS(th)=2–4 V and RDS(on) is specified only at VGS=10 V. A ~4.3–4.6 V comparator high may barely turn on worst-case and cannot guarantee the intended ~2 A dump. Its 90 nC typical gate charge also slows a micro-power comparator output. The ten-resistor bank is pulse-only, with no pulse rating/thermal model.
Corrective action: use a 4.5 V-qualified logic MOSFET with low Qg; add calculated hysteresis; define a hard maximum charger-current pulse and energy; consider a true bidirectional load switch/OVP disconnect rather than dissipating unknown charger power; verify with forced reverse current while converter is both on and off.
Startup path through Q7 body diode is intentional; U3 becomes active near 4 V.
A short at BMS_CELL_PLUS reflects through Q7 to the LM5176. LM5176 hiccup is selected, but guaranteed short-current/thermal behavior depends on corrected current sensing and compensation.
Open BMS terminal leaves the 4.15 V converter regulated and Q7 enabled; no major issue identified, but output-cap precharge/discharge behavior is undefined.
U1 auto-retry can repeatedly stress the eFuse during a hard fault; no fault timer/thermal duty analysis is documented.
Reverse current from BMS to converter is actively blocked by U3/Q7 when powered and above its operating threshold, but native charger energy remains on BMS_CELL_PLUS and must be safely absorbed/disconnected. Current design does not prove that.
Back-power into VBUS is blocked by Q1/U1 architecture in principle; actual reverse leakage and collapse waveforms require measurement.
5. Component-by-component status
Table
Ref(s)
Exact part
Status
Evidence / corrective action
Priority
U1
TPS26630RGE
CONDITIONAL
Correct RGE pin map, voltage range and support wiring; fault SOA/inrush/thermal and automotive surge unverified.
High
U2
LM5176PWPR
FAIL
Correct pin map/topology, but 12 mΩ current limit cannot guarantee 6 A and excludes 8 A; compensation provisional.
Blocker
U3
LTC4359HS8#PBF
PASS/CONDITIONAL
Exact SO-8 H-grade mapping and orientation correct; minimum 4 V and body-diode behavior require system tests.
High
U4
TLV3012AIDBVT
CONDITIONAL
Exact pin map/supply valid near 4.5 V; threshold tolerance and hysteresis unresolved.
High
Q1
NCEP0178AK
CONDITIONAL
100 V DPAK, 12 mΩ max at 4.5 V, correct eFuse orientation; actual library Role Details incorrectly say 8.5 mΩ max (that is 10 V). Verify SOA and hot loss.
High
Q2–Q5
AONS66614
CONDITIONAL
Correct mapping and gate compatibility; 60 V overshoot margin, switching loss and thermal copper unverified.
High
Q6
BSS138
PASS
Correct 1=G,2=S,3=D mapping and low-charge pull-down role; 50 V rating must stay below BGATE transient.
Medium
Q7
AOD508
PASS/CONDITIONAL
4.5 V-qualified, correct source/drain orientation; thermal/reverse tests still required.
High
Q8
NCE6080K
FAIL
No 4.5 V RDS(on) guarantee; VGS(th) max 4 V; high Qg. Replace or drive at 10 V.
Safety/blocker
D1
SMBJ24A-TR
CONDITIONAL
Correct polarity; valid 24 V standoff/38.9 V specified clamp. Automotive surge energy and PCB overshoot not proven.
High
D2,D3
BAT54H,115
PASS/CONDITIONAL
Correct A/K map and bootstrap orientation; 30 V/200 mA adequate in principle; verify ringing.
Medium
L1
XAL7030-222MEC
CONDITIONAL
Electrical ratings plausible; 8 A transient and sealed-cavity temperature need test.
High
R6
12 mΩ, 2 W generic
FAIL
Sets inadequate buck valley limit; exact low-inductance shunt MPN/TCR missing.
Blocker
C5–C8
10 µF/35 V generic
CONDITIONAL/FAIL
Voltage rating passes, effective C/ripple/MPN unknown.
High
C16–C21
22 µF/10 V generic
CONDITIONAL/FAIL
Voltage rating passes, effective C/ripple/MPN unknown.
High
C22–C25
330 µF/6.3 V generic
FAIL
Exact polarized polymer MPN, ESR, ripple, height and lifetime unknown.
~9.1 W only at ~4.48 V and ~2 A; no sustained charge capability/pulse model.
Safety/blocker
6. Thermal and mechanical assessment
The desired 46×80 mm area is 3680 mm². A sealed phone cavity with an insulating thermal pad to a backplate can spread heat, but the pad's thickness/conductivity, contact pressure, backplate material/area, internal ambient, and allowable phone surface temperature are unspecified. At 6 A, even 90% conversion produces ~2.77 W total loss; 85% produces ~4.39 W. At 8 A, 90% produces ~3.69 W and 85% ~5.86 W. These values are too large to approve by junction-to-ambient datasheet numbers alone in a sealed 5 mm cavity. A first prototype needs thermocouples/IR data on U1, U2, Q2–Q5, Q7/Q8, L1, R6, dump resistors and capacitors, plus backplate/surface temperature during thermal soak.
Current layout fails size outright (160×100 mm board; ~104.75×100.79 mm component extent). Although all components are top-side and individual heights appear under 5 mm except unresolved capacitors, no target-envelope placement exists. The DFN/QFN/HTSSOP exposed-pad parts require reflow/hot-plate skill and thermal vias; they do not meet a strong preference for simple iron-only hand soldering. DPAK parts are more hand-solderable but require substantial copper/tab heating.
7. ERC/DRC classification
Schematic ERC: no listed ERC findings were returned for floating pin, no-connect, pin conflict, shorted component, power pin, single-pin net, undriven net, unconnected wire endpoint, or unannotated checks. This is a PASS for logical connectivity only.
Expected/intentional unconnected pins: U1 NC pins, monitoring outputs (IMON/FLT/PGOOD), U2 PGOOD/BIAS, and U3 NC pins are acceptable when left unused as shown; U1 PGTH and MODE are intentionally grounded; U2 ISNS inputs intentionally shorted.
PCB DRC: 141 airwires and the general airwire error list are true PCB incompleteness, not schematic mistakes. The board is not routed and cannot be considered electrically/thermally validated.
Documentation inconsistency: stale part identities in the existing specification/notes are a true review-control error.
8. Required corrective actions before any phone-connected prototype
Replace Q8 or add a proper gate driver; add comparator hysteresis and calculate worst-case trip/reset thresholds.
Define measured Pixel 7 BMS/native-charge current and duration. Replace the dump concept with a rated disconnect/crowbar/energy path if the source can exceed the resistor bank's safe pulse envelope.
Recalculate LM5176 R6 current limit and C13 slope compensation for guaranteed 6 A continuous/8 A transient; verify inductor peak current and MOSFET SOA.
Select exact input/output capacitor MPNs and exact shunt; obtain DC-bias, ESR, ripple, leakage, lifetime and height data.
Complete TI loop-compensation design and simulation/Bode analysis, then load-step testing.
Add a contract-qualified enable or verify a dedicated 15 V trigger that does not load VBUS until negotiation is complete.
Redesign PCB to ≤46×80 mm, all top components, solid/continuous bottom GND where compatible with switching return paths, and a calculated thermal-via/pad/backplate interface. Re-run placement, routing, creepage/current-density, DRC and thermal checks.
Bench sequence: current-limited source; no phone attached; 5/9/15/20/21 V line sweep; startup/hot-plug; overload/short; reverse-current injection; native-charge emulation; oscilloscope capture of VBUS, U1 IN/OUT, SW1/SW2, BMS rail, IDEAL_GATE and DUMP_GATE; only then consider a sacrificial BMS/flex test fixture.
9. Facts not verifiable from the project
Exact automotive PD source/trigger MPN, PDO current at 15 V, negotiation sequence, cable resistance/inductance and surge standard.
Pixel 7 BMS/flex cell-terminal absolute limits, authentication behavior, thermistor/SOC behavior without a cell, and native charger attempted-charge current profile.
Exact MPNs and electrical/mechanical data for all generic capacitors, resistors and the current shunt.
Exact thermal pad material/thickness/conductivity/contact pressure and backplate thermal properties.
Final switching-node overshoot, loop stability, EMI, fault auto-retry temperature, and sealed-cavity junction temperatures.
Safe dump-pulse duration and repetitive duty cycle.
Whether a 6 A continuous battery-terminal load is actually demanded by the Pixel 7; the project previously specified 5 A, while this validation applies the requested 6 A/8 A targets.
Safe to prototype as presently drawn? NO for phone-connected or native-charger-connected use. Credible 6 A continuous? NO, not guaranteed because of the current-limit minimum, unresolved compensation/capacitors, thermal uncertainty and unfinished PCB. Credible 8 A transient? NO because the 12 mΩ buck current limit excludes 8 A even before ripple and the capacitor bank provides only short nominal support. Fits 46×80×5 mm? NO as currently laid out; height is also unverified due to placeholder bulk capacitors. A corrected design may become feasible at 15 V/3 A, but it requires the blocker corrections and bench evidence listed above.
R6: 12 mΩ/2 W placeholder → 10 mΩ ±1%, 3 W, 2512 metal-element HoJLR2512-3W-10mR-1%. CS/CSG must use separate Kelvin traces directly to the two resistor pad ends. A true four-terminal 10 mΩ/≥3 W part was not available in the Flux library; Kelvin routing is therefore a mandatory PCB constraint.
C13: 75 pF → 110 pF C0G, 5%, 50 V, recalculated for 2.2 µH and 10 mΩ by scaling LM5176 datasheet Eq. 26.
Q8: NCE6080K → AOD508, 30 V DPAK, RDS(on) max 4.5 mΩ at VGS=4.5 V, Qg max 23 nC. Recorded G/D/S nets were restored: DUMP_GATE / DUMP_DRAIN / GND.
R26 added:10 MΩ, 1% from TLV3012 OUT to IN+ for explicit positive-feedback hysteresis (approximately 80 mV referred to BMS rail; final trip/reset tolerance must be measured).
TPS26630 interlock: R2 887 kΩ, R3 40.2 kΩ, R4 49.9 kΩ. Nominal rising UVLO is 13.014 V and OVP is 23.497 V, preventing significant board loading during 5 V/9 V PD negotiation while accepting a negotiated 15 V rail.
LM5176 compensation finalized as the schematic starting network: R11 10 kΩ, C14 33 nF, C15 560 pF. Compensation zero is about 482 Hz and high-frequency pole about 28.4 kHz. This follows the LM5176 Type-II procedure and TI's 300 kHz design starting values; because the exact closed-loop plant and PCB parasitics cannot be proven in schematic ERC, injection/Bode and load-step verification remain mandatory.
Input MLCCs C5–C8: exact Yageo CC1210KKX7R9BB106, 10 µF, 50 V, X7R, 1210. Four in parallel; effective capacitance at 15–21 V must be taken from the vendor DC-bias curve rather than nominal value.
Output MLCCs C16–C21: exact Yageo CC1210KKX7R8BB106, 10 µF, 25 V, X7R, 1210, six in parallel.
Output bulk C22–C25: exact KEMET T520D337M006ATE025, 330 µF, 6.3 V polymer tantalum, 20%, CASE-D/7343, 25 mΩ ESR, low-profile molded package; polarity is mandatory. Nominal bank is 1320 µF polymer plus 60 µF ceramic.
Corrected stale Q1 documentation: NCEP0178AK is 8.5 mΩ max at 10 V and 12 mΩ max at 4.5 V; TPS26630 normally drives it near 10.2 V.
12.2 Recalculated operating point
At 15 V → 4.15 V, 300 kHz, 2.2 µH, ideal buck ripple is 4.548 A p-p. At 8 A, valley/peak are approximately 5.726 A / 10.274 A. With the 66 mV minimum LM5176 buck-valley threshold and R6 at +1% (10.1 mΩ), minimum valley limit is 6.535 A, equivalent to 8.809 A average at nominal inductance; corresponding peak is about 11.083 A. This provides nominal tolerance/ripple margin above the 8 A transient target, while remaining below L1's 18 A typical 30%-drop saturation rating. Minimum-inductance, hot-current-threshold, layout-noise, and transient tests remain required.
Power: 6 A = 24.9 W, requiring 1.844 A at 90% or 1.953 A at 85% from 15 V. 8 A = 33.2 W, requiring 2.459 A at 90% or 2.604 A at 85%. A 15 V/3 A PD contract remains required. TPS26630's 2.77 A nominal limit is adequate at nominal 15 V but close at 8 A/85%; source droop and tolerances must be tested.
First-order RMS losses using calculated ripple: R6 is 0.377 W at 6 A and 0.657 W at 8 A (0.381/0.664 W at +1% R), comfortably below 3 W but thermally concentrated. Q7 AOD508 at 4.5 mΩ max is approximately 0.170 W / 0.296 W. L1 at 15.07 mΩ max is approximately 0.568 W / 0.990 W, before AC/core loss. Each bridge FET, copper, switching, eFuse and capacitor ESR add loss. System heat remains roughly 2.8–5.9 W over the efficiency range and is CONDITIONAL in the sealed 5 mm envelope.
12.3 Revalidation by block
Table
Block
Revised status
Evidence / limitation
15 V PD startup interlock
PASS/CONDITIONAL
TPS26630 UVLO now nominally 13.0 V, so 5/9 V negotiation states do not enable the converter. The board still cannot verify PDO current or telemetry; use a dedicated, verified 15 V/3 A trigger.
Input eFuse/reverse block
CONDITIONAL
TPS26630/Q1 topology and ratings remain valid; 2.77 A nominal input limit, 23.5 V OVP and 24 V TVS are coherent. Hot-plug, cable inductance, repeated fault SOA and surge standard remain bench items.
LM5176 current limit
PASS/CONDITIONAL
10 mΩ gives 8.809 A minimum average limit at nominal L using the datasheet's 66 mV minimum valley threshold and +1% shunt. Kelvin routing and worst-case L/temperature/noise testing are mandatory.
Inductor
CONDITIONAL
10.274 A peak at the 8 A operating point and 11.083 A at minimum current limit are below 18 A typical Isat; 0.99 W worst first-order DCR loss at 8 A requires thermal validation.
Compensation
CONDITIONAL
Exact 10 kΩ/33 nF/560 pF network is no longer a placeholder and follows TI's method. It is not releasable without measured phase/gain margin and load-step response on the final PCB.
Input/output capacitors
PASS/CONDITIONAL
Exact MPNs, voltage, ESR class and package are now recorded. Verify Yageo DC-bias curves, KEMET ripple/lifetime, polarity, and actual component height/fit.
LTC4359/Q7 reverse blocking
PASS/CONDITIONAL
Orientation rechecked: converter on IN/SOURCE/Q7 source, BMS on OUT/Q7 drain. LTC4359 4–80 V, fast reverse turnoff, and AOD508 4.5 V gate rating are suitable. A single MOSFET does not block its forward body diode during shutdown.
BMS OVP/Q8 drive
PASS/CONDITIONAL
Q8 is now guaranteed enhanced at 4.5 V and has DPAK thermal/current margin; R26 adds hysteresis. The shunt bank remains approximately 2.2 Ω/~2 A and is not a sustained charger-energy sink.
Reverse current into the converter is blocked independently by LTC4359/Q7, and the BMS node has an independent OVP shunt. However, no verified Pixel 7 BMS charge-current/time profile exists, and the present ~9 W resistor bank cannot safely absorb an arbitrary sustained charger attempt. Non-destructive native-USB insertion therefore cannot yet be guaranteed without measured limits or a separately rated regenerative/dissipative sink. Do not rely on undocumented BMS FET action.
Mechanical/thermal envelope
UNATTEMPTED in this task
Per scope, PCB was not resized or laid out. The existing board still fails 46×80 mm and is not phone-ready. Components remain intended top-side with bottom GND thermal plane in a later layout task.
12.4 Fresh schematic/ERC review
Fresh schematic review at 2026-08-06 16:41 UTC returned no listed ERC, decoupling, resistor-power, capacitor-voltage, or pull-up/down findings in the requested categories. Critical net inspection confirmed the revised UVLO/OVP ladder, CS shunt, slope/COMP networks, LTC4359/Q7 ideal-diode path, and Q8/R26 BMS shunt connections. This is a logical-connectivity PASS, not proof of analog stability or phone safety.
12.5 Revised verdict
Safe for current-limited bench prototyping without the phone: CONDITIONAL YES. Use an isolated/current-limited 15 V supply or programmable PD source, electronic load, oscilloscope, thermocouples, and forced reverse-current source. Start below 1 A and qualify startup, short circuit, 6 A thermal soak, 8 A pulses, Bode/load-step response, and BMS-node overvoltage clamp energy.
Ready to connect to the phone or native USB charger: NO. The independent reverse block is improved and the Q8 drive defect is corrected, but the native-charge energy/current profile is unknown and the shunt is not rated for arbitrary sustained charging. The PCB also remains outside the required envelope and unrouted. Phone connection is prohibited until charge-back testing on a sacrificial BMS fixture establishes a bounded pulse envelope or the design receives a rated sink/regenerative path, followed by target-envelope layout/thermal validation.
13.1 Scope and architecture frozen for this review
This section is a fresh read-only audit of the actual current project: 72 components, 36 nets, all component properties, all net memberships, all 14 BOM groups, and current ERC/review state. No schematic or PCB objects were changed. The external architecture is now: an automotive USB-PD charger and fixed 15 V / 3 A trigger near the dashboard; approximately 2 m one-way twisted copper pair, preferably 0.75 mm²; direct solder into PCB pads through the removed speaker opening; no connector and no PD controller on this PCB; TPS26630 plus LM5176 produces approximately 4.15 V for the separated original Pixel 7 BMS/flex. Targets are 6 A continuous and 8 A transient. Eventual board envelope is 46 × 80 × 5 mm, components top-side, bottom GND plane thermally coupled to the backplate through an electrically insulating pad. LTC4359 and comparator/Q8/shunt mitigation remain. Accidental native USB charger insertion is prohibited misuse and survival is not guaranteed.
13.2 Fresh inventory/connectivity result
The power path is coherent and MOSFET orientations are correct by net membership: TP1/VBUS_TAP → Q1 source, Q1 drain → EFUSE_IN/U1 IN → U1 OUT/VIN_PROTECTED → Q2/Q3, L1, Q4/Q5 → CONVERTER_4V15 → Q7 source/LTC4359 IN+SOURCE → Q7 drain/BMS_CELL_PLUS. Q8 is a low-side shunt switch (DUMP_DRAIN → Q8 drain, Q8 source → GND). Bootstrap diodes/capacitors, 10 mΩ CS/CSG shunt, FB divider, UVLO/OVP ladders, compensation, soft start, VCC bypass, TLV3012 reference bypass, gate pull-down and positive feedback are all logically connected. U1 NC pins, U2 PGOOD/BIAS, U3 NC pins and unused status/monitor pins are intentionally no-connect.
Direct-wire pads do exist schematically: TP1 is VBUS input, TP2 GND input, TP3 BMS cell+, TP4 BMS cell−. They are represented as 4 mm test-point footprints, not purpose-built wire pads. This satisfies logical connectivity but does not represent strain relief. Add two plated mechanical tie holes/slots or adhesive/lacing anchor geometry beside TP1/TP2 in layout; do not add a connector. Use large teardropped copper lands, solder-mask relief, and duplicated vias/pour transitions sized for the cable. This is a PCB-layout requirement, not a missing electrical part.
Fresh ERC/design-review query returned zero listed findings in Electrical Rule Checks, Passive Components, and Component Review Checks at 17:23 UTC. This is a logical-connectivity PASS only; it does not validate stability, hot-plug waveforms, thermal behavior, or native-charge survival.
13.3 Two-metre cable calculation
Assumptions: 2 m one-way / 4 m loop, copper resistivity 0.017241 Ω·mm²/m at 20°C, temperature coefficient 0.00393/°C, and 85°C conductor margin (+25.545% resistance). Input current is reflected from 4.15 V output at 90% and 85% efficiency.
Table
Wire
Loop R, 20°C
Loop R, 85°C
6 A output IIN
Drop/loss at 85°C
8 A output IIN
Drop/loss at 85°C
0.50 mm²
137.9 mΩ
173.2 mΩ
1.844–1.953 A
0.319–0.338 V / 0.589–0.660 W
2.459–2.604 A
0.426–0.451 V / 1.047–1.174 W
0.75 mm²
92.0 mΩ
115.4 mΩ
1.844–1.953 A
0.213–0.225 V / 0.393–0.440 W
2.459–2.604 A
0.284–0.301 V / 0.698–0.783 W
At 20°C, corresponding drops are 0.254–0.269 V and 0.339–0.359 V for 0.5 mm², and 0.170–0.180 V and 0.226–0.239 V for 0.75 mm². Use 0.75 mm² twisted pair. The hot 8 A-output case still presents about 14.70 V at the PCB before source tolerance/contact losses, comfortably above the 13.0 V nominal eFuse UVLO. Verify the actual trigger maintains its PDO under this load.
13.4 Input inductance, ringing, inrush and TVS
The exact cable inductance is not specified; a 2 m twisted pair is normally in the low-microhenry range and stores only microjoules at 2.6 A, but its resonance with low-ESR ceramic input capacitance can generate a severe hot-plug overshoot if the source is stiff. SMBJ24A provides 24 V standoff, 26.7–29.5 V breakdown and 38.9 V maximum clamp at 16 A on a 10/1000 µs pulse, 600 W non-repetitive. This is coherent with 60 V-rated U1/U2/bridge FETs, but it is not an automotive load-dump qualification and its lead/trace inductance matters.
TPS26630 documentation requires at least 0.1 µF at IN_SYS and recommends at least 1 µF local input capacitance for surge/transient control. The schematic has only C1=100 nF on VBUS_TAP. Therefore:
Actual missing schematic part — HIGH: add 1 µF, 50 V, X7R, 1206, e.g. Yageo CC1206KKX7R9BB105, directly between VBUS_TAP/IN_SYS and GND beside U1/D1. Keep C1=100 nF in parallel.
PCB-layout requirement — HIGH: place D1 and the 1 µF capacitor at the TP1/TP2 entry with a very short clamp loop; keep Q1/U1 and Q6 gate-pulldown loop compact.
Bench-test requirement — HIGH: hot-plug with the real 2 m cable and trigger while probing directly at TP1 and U1 IN/OUT. Test repeated connect/disconnect at no load, 6 A output and 8 A pulses, including warm cable/source. Acceptance: VBUS_TAP remains below device limits, no sustained ringing, no PD reset, and D1/U1 temperatures remain bounded.
Conditional damping, not an automatic part: do not add a large undamped MLCC bank ahead of U1. If measured ringing exceeds approximately 24 V or persists, fit a populated option for a series-RC damper (starting experiment: 1–2.2 Ω pulse-rated resistor in series with 1–4.7 µF/50 V X7R) or a 22–47 µF, ≥35 V electrolytic/polymer with useful ESR. Final values must come from measured cable/source impedance. This is presently a bench-tuned option, not a proven required BOM item.
The four 10 µF/50 V input MLCCs are after U1. With C2=10 nF, TPS26630 equations give approximately 3.12 ms output ramp at 15 V; for nominal 40 µF this is about 0.19 A inrush, before DC-bias derating. Thus the post-eFuse bank itself does not require more bulk for startup. U1 MODE is grounded, so overloads auto-retry after current limiting/thermal shutdown; repeated hard faults must be temperature-tested.
13.5 LM5176, current limit, inductor and switch margin
At 15 V → 4.15 V, 300 kHz and 2.2 µH nominal, calculated ripple is 4.55 A p-p. At 6 A, valley/peak are about 3.73/8.27 A; at 8 A, 5.73/10.27 A. LM5176 HTSSOP buck valley threshold is 66/80/94 mV. With R6=10 mΩ +1%, minimum valley limit is 6.535 A, corresponding to approximately 8.81 A average at nominal L. The current target is therefore supported nominally, but the ±20% inductor and threshold/temperature/noise extremes require hardware verification. R6 dissipation including ripple is approximately 0.38 W at 6 A and 0.66 W at 8 A; the 3 W part has rating margin, but Kelvin routing is mandatory.
L1 XAL7030-222MEC is 2.2 µH ±20%, 15.07 mΩ max DCR, 18 A typical Isat (30% inductance drop), 10 A Irms for 20°C rise, 12.9 A Irms for 40°C rise, and 3.1 mm maximum height. The schematic Role Details incorrectly call 12.9 A “Isat”; that is stale metadata. Peak current is below 18 A typical, but 8 A RMS plus ripple yields about 0.99 W DCR loss before core loss and sealed-phone derating. Status: electrically plausible, thermally conditional.
Q2–Q5 AONS66614 are correctly oriented 60 V logic-level DFN5×6 MOSFETs, 2.9 mΩ max at 10 V, 4.1 mΩ max at 4.5 V, 38 nC max Qg at 4.5 V, and approximately 1.6°C/W junction-to-case only with a strong thermal path. Their 60 V rating is acceptable behind the TVS but measured switch-node overshoot, dead-time loss and hot RDS(on) remain mandatory bench items. No electrically necessary series gate resistors are missing: LM5176 directly drives the four gates per its intended topology. Add 0 Ω/2.2–4.7 Ω gate-resistor footprints only as optional EMI-tuning provisions if layout space allows; do not count them as required parts.
13.6 Capacitors, compensation and output transients
The current final network is four Yageo 10 µF/50 V 1210 input MLCCs, six Yageo 10 µF/25 V 1210 output MLCCs, and four KEMET T520D337M006ATE025 330 µF/6.3 V, 25 mΩ polymer tantalums. Nominal COUT is 1380 µF. The LM5176 10 kΩ/33 nF/560 pF Type-II network exactly matches TI's published starting values (zero ≈482 Hz, pole ≈28.4 kHz), but TI explicitly requires laboratory tuning for the actual plant. Four nominal 25 mΩ polymers in parallel yield about 6.25 mΩ before ceramic contribution and layout.
For a sudden 2 A deficit, ideal capacitive droop of 0.2 V occurs in about 138 µs; ESR contributes an immediate step of roughly 12.5 mV for the polymer bank alone. The bank cannot independently sustain millisecond 8 A bursts; the converter/source must respond. Required bench criteria: Bode injection at minimum/nominal/maximum input and representative loads, ≥45° phase margin and ≥10 dB gain margin preferred; 0↔6 A and 6↔8 A load steps; verify BMS rail remains within the allowed cell-terminal band; measure capacitor ripple temperature.
Metadata/orderability findings:
C22–C25 are polarized polymer tantalums but are still marked Part Type: Non-Polarized Capacitor. This is contradictory metadata and risks assembly polarity mistakes. Correction priority: HIGH before BOM release.
C12=100 nF has no voltage rating. Specify ≥16 V X7R 0805. C1/C2/C9–C15/C26–C28 and most divider/compensation resistors have values/packages but no exact MPN. They are electrically conventional and orderable by specification, but the BOM is not procurement-frozen. Use a consistent AEC-Q200-capable series where practical: Yageo RC0805FR for 1% resistors, RT0805BR for 0.1% dividers, CC0805KRX7R for X7R capacitors, and CC0805JRNPO for C0G parts, selecting the exact value/voltage suffix. This is a BOM-release requirement, not a missing topology part.
R17–R25 and R5 are generic 22 Ω/1 W 2512 parts with no MPN and are intentionally pulse/intermittent only. If retained, specify Vishay CRCW251222R0FKEG or equivalent 22 Ω, 1 W, 1%, 2512 and validate pulse energy; ten parts provide only ~2.0 A / ~9.1 W near 4.48 V.
13.7 Ideal diode, OVP, startup, interruption and faults
LTC4359/Q7 orientation is correct. Q7 AOD508 is 30 V, 4.5 mΩ max at 4.5 V and 23 nC max gate charge; estimated conduction loss is about 0.17 W at 6 A and 0.30 W at 8 A before hot RDS(on). LTC4359's approximately 300–500 ns reverse turnoff supports charge-back isolation, but its single MOSFET body diode still permits forward converter-to-BMS startup and shutdown feed-through in that direction. This is intentional.
U4/Q8/shunt topology is coherent. Q8 is now 4.5 V-qualified and R16 holds it off before U4 is valid; R26 adds explicit hysteresis. However, the ten-resistor shunt is not a sustained charger sink. Under the finalized assumption, native USB insertion is prohibited misuse / accepted risk, and survival is not guaranteed. Preserve the circuit as mitigation only; do not describe it as charger-safe.
On valid external startup, the eFuse waits for approximately 13 V, then ramps its output and LM5176 soft-starts via C12. Loss of the PD contract or cable interruption collapses the input; Q7 blocks BMS-to-converter reverse current once the controller reacts, while output capacitors and body-diode dynamics determine the short interruption waveform. The board has no energy storage capable of riding through a meaningful PD dropout. Bench-test requirement: force 15→9→5→0 V steps and brief interruptions while monitoring VBUS_TAP, VIN_PROTECTED, CONVERTER_4V15, BMS_CELL_PLUS and IDEAL_GATE; confirm clean restart and no BMS overvoltage/negative excursion.
For an output short, LM5176 cycle limiting/hiccup and TPS26630 2.77 A nominal input limit provide layered protection. U1's documented hard-short response includes fast trip and subsequent current limiting/thermal regulation with auto-retry because MODE is grounded. This is suitable as a protection concept but repeated-fault SOA in the sealed thermal environment is unproven.
13.8 Classified action list
Table
Classification
Item
Exact recommendation
Priority
Actual missing schematic part
U1 local input capacitor
1 µF, 50 V, X7R, 1206; Yageo CC1206KKX7R9BB105, VBUS_TAP to GND at U1/D1
High
PCB-layout requirement
Input cable strain relief
Two non-electrical plated tie holes/slots or adhesive/lacing anchor adjacent to TP1/TP2; large teardropped pads and copper pours
High
PCB-layout requirement
Power/thermal geometry
Kelvin R6; compact gate/switch loops; D1/U1 entry clamp loop; exposed-pad thermal vias; continuous bottom GND except where switching return control requires; insulated backplate thermal pad
Blocker before layout release
BOM-release requirement
Polarized bulk metadata
Mark C22–C25 polarized and preserve pin polarity; exact KEMET MPN already chosen
High
BOM-release requirement
Generic support passives
Assign exact MPNs/series and ratings; at minimum give C12 ≥16 V and exact 22 Ω dump-resistor MPN
Medium/High
Bench-test requirement
Input ringing/damping
Real 2 m cable hot-plug captures; populate RC/electrolytic damping only from measurement
High
Bench-test requirement
Stability/transient/thermal
Bode, load steps, 6 A soak, 8 A pulses, short/auto-retry, PD step/dropout, reverse-current injection
Blocker before phone use
Accepted risk
Native USB charger insertion
Explicitly prohibited misuse; survival not guaranteed; shunt is mitigation only
Permanent unless architecture changes
Optional tuning provision
MOSFET gate damping
0 Ω default footprints permitting 2.2–4.7 Ω after EMI/ringing measurements
Low
No separate board fuse is electrically mandatory if the external automotive PD charger is branch-fused and the 2 m feed is protected at its dashboard source; document the source fuse rating and placement. If that cannot be guaranteed, add an external/source-end 3 A automotive fuse near the charger, not a hot high-resistance PTC inside the phone. TP1/TP2/TP3/TP4 already provide the electrically necessary test access; additional schematic test points are optional.
13.9 Stale/contradictory metadata
Project description still says 4.5–21 V input and “USB-C VBUS-powered”; final architecture is a fixed external 15 V trigger and direct two-wire feed.
TP1/TP2 Role Details say “Phone USB-C assembly” wire landing; they now represent the dashboard-trigger cable.
L1 Role Details say 12.9 A Isat; datasheet identifies 18 A typical Isat and 12.9 A as 40°C-rise Irms.
C22–C25 are marked non-polarized despite exact polarized polymer tantalum MPNs.
Most generic support passives lack exact MPNs; BOM grouping/pricing therefore cannot be treated as a released procurement list.
These are documentation/BOM-control defects, not connectivity defects, but should be corrected during the next schematic correction pass.
13.10 Final verdict
Electrically complete enough to proceed to schematic correction: YES. The architecture and critical net topology are coherent, and fresh ERC is clean. The one clear missing electrical part is the TPS26630-recommended 1 µF local input capacitor. Metadata/polarity and procurement details also require correction.
Ready for a current-limited bench prototype after that correction: CONDITIONAL YES. Prototype only with the external fixed 15 V trigger or a controlled 15 V supply, the real cable, electronic load, oscilloscope, Bode equipment and thermal instrumentation. Do not connect the phone initially.
Ready for final target-envelope layout: NO. The current board is still 160 × 100 mm with a 104.75 × 100.79 mm component extent, 51 vias and unfinished routing, versus the eventual 46 × 80 × 5 mm requirement. Strain relief, Kelvin/current loops, thermal-via strategy, top-side fit and backplate interface remain layout work.
Ready for phone/native-charger use: NO. Phone connection requires successful stability, hot-plug, dropout, reverse-current, short-circuit and sealed-cavity thermal tests on a sacrificial BMS fixture. Native USB charger insertion remains prohibited misuse and survival is not guaranteed.
14. Schematic metadata close-out and fresh validation (2026-08-07 19:38 UTC)
14.1 In-place metadata corrections
No connectivity, architecture, or PCB-layout objects were changed.
C22–C25: corrected from contradictory Non-Polarized Capacitor metadata to Polarized Capacitor. Procurement is frozen to KEMET T520D337M006ATE025, 330 uF, 6.3 V, ±20%, polymer-tantalum, CASE D / 7343, 25 mΩ ESR. The KEMET datasheet URL and Allow Substitutes: No are recorded. Role Details explicitly define P1 positive on CONVERTER_4V15 and P2 negative on GND. The existing exact SMD_7343_2828Metric footprint was preserved; Flux warns that this exact case footprint is outside the generic-capacitor autocomplete list, but read-back confirms it remains assigned.
C12: standardized to 100 nF, 16 V, ceramic X7R, hand-solderable 0805, Soft Start; Role Details identify the U2 SS-to-GND function and approximately 16 ms nominal startup.
L1: canonical ratings now distinguish Saturation Current = 18 A typical at 30% inductance drop from Current Rating = 12.9 A for 40°C rise (10 A for 20°C rise). Role Details retain 2.2 uH ±20%, 15.07 mΩ maximum DCR, and 3.1 mm maximum height.
C3: standardized to Yageo CC1206KKX7R9BB105, 1 uF, 50 V, X7R ceramic, ±10%, hand-solderable 1206, with Decoupling role for TPS26630 IN_SYS/VBUS_TAP. It remains connected from VBUS_TAP to GND.
R5 and R17–R25: the previously generic procurement-critical dump bank is frozen to Vishay CRCW251222R0FKEG, 22 Ω, 1%, 1 W, 2512, Allow Substitutes: No. Existing values and footprints were preserved. This exact-part selection does not upgrade the bank into a sustained charger sink.
Previously frozen critical passives were read back unchanged: C5–C8 Yageo 10 uF/50 V/1210 input MLCCs, C16–C21 Yageo 10 uF/25 V/1210 output MLCCs, and R6 10 mΩ/3 W/2512 shunt with Kelvin-routing requirement.
14.2 Fresh connectivity and ERC/design review
Fresh review timestamp: 2026-08-07T19:38:35.802Z.
Electrical Rule Checks, Passive Components, and Component Review Checks returned zero listed findings.
Critical net membership was re-read after the property edits. The chain remains: TP1/VBUS_TAP → Q1/U1 EFUSE_IN → U1 VIN_PROTECTED → LM5176 bridge SW1/L1/SW2 → CONVERTER_4V15 → LTC4359/Q7 → BMS_CELL_PLUS/TP3.
C3 remains VBUS_TAP-to-GND; C12 remains U2 SS-to-GND; C22–C25 P1 remain on CONVERTER_4V15 and P2 on GND.
CS_HIGH still joins the bridge current path, R6, and U2 CS; R6's other end and U2 CSG remain on GND. DUMP_GATE remains U4 OUT/Q8 gate/R16/R26; DUMP_DRAIN remains Q8 drain plus all ten dump-resistor low sides; all ten resistor high sides remain on BMS_CELL_PLUS.
The metadata-only edit therefore introduced no logical connectivity change. This is an ERC/logical-membership pass, not analog, thermal, EMI, stability, cable hot-plug, or phone-safety proof.
14.3 Remaining risks and readiness verdict
Bench prototype with isolated/current-limited fixed 15 V source or verified 15 V/3 A PD trigger:CONDITIONAL YES. Use the real approximately 2 m 0.75 mm² twisted two-wire feed, electronic load, oscilloscope/Bode equipment, and thermal instrumentation. Qualify hot-plug/ringing, PD dropout, Bode margin, 0↔6 A and 6↔8 A load steps, short/auto-retry, reverse-current injection, and 6 A thermal soak before connecting a phone.
Phone or native-USB use:NO. The original Pixel BMS/flex remains the intended endpoint and LTC4359 reverse blocking plus the OVP/shunt are retained, but the Pixel native-charge energy/current profile is still unknown. The approximately 2.2 Ω / 9 W dump bank is pulse/intermittent mitigation only and cannot guarantee survival under sustained charger insertion.
Manufacturing/layout release:NO. PCB layout was explicitly outside this task. Target-envelope fit, direct-wire strain relief, short TVS/C3 clamp loop, R6 Kelvin geometry, switch-loop control, thermal vias/backplate interface, routing, and final DRC remain unresolved.
Procurement status: the specifically flagged power capacitors, C3, L1 ratings, shunt, converter MLCC banks, and dump-resistor bank are now materially frozen. Many low-power conventional support passives still lack exact MPNs; they are not topology blockers but remain a formal full-BOM release item if zero-substitution procurement is required.
Readiness verdict: schematic metadata and logical connectivity are ready for controlled bench-prototype preparation; the design is not ready for phone connection, native-charger exposure, final target-envelope layout release, or manufacturing release.
15. Sustained/transient current close-out (latest audit)
15.1 Final current-budget correction
The final external architecture is a regulated 15 V / 3 A USB-PD trigger near the vehicle charger and an approximately 2 m two-wire feed. At 85°C, a 0.75 mm² copper pair has approximately 115.4 mΩ loop resistance. The conservative 8 A-output case is 33.2 W; at 14.70 V at the PCB and 85% converter efficiency it requires 2.657 A input. The 6 A-output case requires 1.993 A input under the same assumptions. A 0.50 mm² pair has approximately 173.2 mΩ hot loop resistance and materially worse loss; 0.75 mm² remains the preferred wire.
The previous TPS26630 R1=6.49 kΩ setting produced 2.77 A nominal but only about 2.58 A at the datasheet's -7% current-limit tolerance, so it could clip the conservative 8 A transient. R1 is now 6.24 kΩ, 1%, giving 2.885 A nominal, 2.683 A minimum, and approximately 3.087 A maximum. This closes the calculated worst-case transient margin without replacing the TPS26630. The maximum setting slightly exceeds 3 A, so the external trigger must be a genuine 15 V / 3 A source with normal transient tolerance; a 15 V / 2 A PDO is prohibited. At 2.657 A and the TPS26630's 53 mΩ worst hot on-resistance, internal-path conduction is about 0.37 W, requiring the exposed-pad thermal-via implementation already documented.
TPS26630 alternatives were reconsidered. TPS26631 adds a 2× pulse-overcurrent mode but does not improve the continuous integrated-path rating and would permit excessive source pulses; fixed-clamp TPS26632/33 variants conflict with the selected adjustable 23.5 V OVP behavior. A controller plus external series FET would add parts, validation risk and area without a demonstrated need at the calculated 2.0 A continuous / 2.66 A transient input. The retained TPS26630 is therefore the topology-compatible selection.
15.2 Final selected power-stage parts and margins
Table
Function
Final selection
Datasheet-backed margin / limitation
Input eFuse
TPS26630RGE + R1 6.24 kΩ
4.5–60 V, 6 A family capability, 31 mΩ nominal path; 2.683 A minimum programmed limit exceeds 2.657 A calculated transient input. Exposed-pad VQFN is unavoidable for protection/thermal density.
Controller
LM5176PWPR
15 V-to-4.15 V four-switch topology retained; 7.35 V nominal VCC gate drive, 1.8 A source/2.2 A sink drivers, 66 mV minimum HTSSOP buck-valley threshold. Exposed-pad HTSSOP requires reflow/hot plate and thermal vias.
Bridge FETs Q2–Q5
AONS66614
60 V; 2.9 mΩ max at 10 V, 4.1 mΩ max at 4.5 V; 38 nC max Qg at 4.5 V. DFN5×6 bottom pad is unavoidable for switching loss/height; validate overshoot and hot RDS(on).
Current shunt
HoJLR2512-3W-10mR-1%
10 mΩ, 3 W, 1%; approximately 0.38 W at 6 A and 0.66 W at 8 A including ripple. Kelvin sense routing mandatory.
Inductor
XAL7030-222MEC
2.2 µH ±20%, 18 A typical Isat, 10 A/12.9 A thermal-current ratings, 15.07 mΩ max DCR, 3.1 mm height. Calculated 8 A peak about 10.27 A; thermal validation remains required.
Ideal-diode MOSFET Q7
AOD508
30 V DPAK, 4.5 mΩ max at 4.5 V, 23 nC max Qg; about 0.17 W at 6 A and 0.30 W at 8 A before hot derating. Side-leaded and comparatively hand-solderable.
OVP/dump MOSFET Q8
AOD508
Replaced the failed 10 V-only NCE6080K; guaranteed 4.5 V enhancement and lower Qg. Dump bank remains pulse/intermittent mitigation only.
Input capacitors
4× Yageo CC1210KKX7R9BB106 + C3 CC1206KKX7R9BB105
Exact 50 V X7R parts; account for DC-bias effective capacitance. C3 provides local U1 input capacitance at VBUS_TAP.
60 µF nominal ceramic plus 1320 µF polymer; KEMET parts are 6.3 V, 25 mΩ ESR, polarized CASE-D/7343. Bank supports fast edge only; converter must carry sustained 8 A pulses.
Dump bank
10× Vishay CRCW251222R0FKEG
2.2 Ω equivalent, approximately 9.1 W at 4.48 V; not a sustained charger sink. Accidental native USB charging remains prohibited misuse.
15.3 Failed/marginal-item disposition
All component failures identified in the earlier report now have a schematic disposition: Q8 was replaced by AOD508; R6/C13 were recalculated; exact input/output capacitors and dump resistors were assigned; C22–C25 polarity was corrected; C3 local input capacitance was added; LM5176 compensation has an exact starting network; U1 current-limit margin was closed with R1=6.24 kΩ; stale cable, inductor and MOSFET metadata was corrected. The LTC4359 reverse-blocking stage and OVP/shunt mitigation are retained.
Remaining limitations are validation limits rather than unidentified component failures: measured loop gain/load-step response, switch-node overshoot, hot-plug ringing with the real cable, 6 A sealed-cavity thermal soak, 8 A pulse duration, repeated-short auto-retry temperature, and reverse-current/OVP testing on a sacrificial BMS fixture. Native USB charging is explicitly prohibited misuse and is not guaranteed survivable. PCB fit, placement, thermal geometry and routing were not modified in this task.
15.4 Simulation and bench criteria
A credible full-power simulation is not practical from the present schematic because the library power MOSFETs, TPS26630, LTC4359, polymer capacitors and magnetic core do not provide a complete verified common SPICE model set, while cable/source impedance and Pixel BMS load dynamics are unknown. A simplified ideal model would conceal the dominant switching, current-limit, hot-plug and thermal risks. Required bench acceptance remains: verified 15 V/3 A contract; real 2 m 0.75 mm² cable; 0↔6 A and 6↔8 A load steps; BMS rail maintained within the established cell-terminal band; ≥45° phase margin and ≥10 dB gain margin preferred; 6 A thermal soak with all junction/case temperatures derated; 8 A pulse test over the intended pulse duration; 15→9→5→0 V dropouts; hot-plug ringing below device absolute maximums; output short/auto-retry; reverse-current injection; and OVP dump pulse-energy verification.
15.5 Latest readiness verdict
Component/current capability: PASS/CONDITIONAL. No known failed component remains unaddressed, and every power-path component has a calculated rating or loss margin for the stated operating point. Controlled bench prototype: CONDITIONAL PASS after fresh ERC/connectivity confirmation. Phone connection, native-charger exposure, target-envelope layout release, and manufacturing release: FAIL/PENDING until the listed bench and PCB-layout validations are completed.
1. Executive verdict
Priority blockers
2. Inspected design state
3. Power budget and limits at 15 V
First-order losses
Capacitor energy/transient support
4. Functional-block audit
4.1 PD-trigger handoff and 5 V negotiation — CONDITIONAL / HIGH
4.2 Input TVS/eFuse/UVLO/OVP/inrush — CONDITIONAL / HIGH