Pixel 7 Car Power Mod
Fix the remaining BOM metadata issues, then rerun the schematic validation.
Thought for 5 sec
I’ll correct the remaining BOM/property inconsistencies identified in the audit, freeze the necessary procurement specifications, and then rerun the full schematic/ERC validation against the final 15 V external-trigger architecture.
Worked for 1 min 7 sec
The metadata correction and revalidation could not run because no ACUs are currently available. No changes were made during this attempt.
Remaining work:
- Correct C22–C25 polymer-tantalum polarity/package metadata.
- Add C12 voltage, dielectric and role specifications.
- Correct L1’s 18 A typical saturation versus 12.9 A thermal-current metadata.
- Standardize C3’s capacitor-type and role properties.
- Freeze remaining procurement-critical passive specifications.
- Rerun connectivity, critical-net and ERC validation.
- Update the validation report with the final readiness verdict.
Fix and validate
Prioritize BOM fields
List BOM issues
Check ERC/DRC
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Project Specification
Project Overview
Status: schematic protection revision complete; prototype-only pending loop/thermal/transient validation. Low-profile Google Pixel 7 USB-C battery emulator that replaces only the electrochemical cell while retaining the original battery BMS/flex. No lithium cell is present.
Preserved Interfaces and Mechanical Envelope
- TP1 = VBUS direct solder pad; TP2 = GND direct solder pad.
- TP3 = BMS cell-positive direct solder pad; TP4 = BMS cell-negative direct solder pad.
- Pad-only interfaces: no connectors and no added CC/PD connection.
- PCB maximum 46 × 80 mm; total installed height ≤5 mm.
- The Pixel USB-C assembly remains the sole PD/PPS negotiator; this board only taps negotiated VBUS/GND.
Regulated Output Requirement
- Input: 4.5–21 V continuous negotiated VBUS.
- Output: 4.15 V battery-equivalent rail to the original BMS cell pads.
- Desired full-performance output: 5 A continuous (20.75 W) after source, converter, thermal, and BMS validation.
- No sustained backfeed into VBUS when input collapses or protection disables.
Revised Architecture
TP1 VBUS → SMBJ24A TVS → CSD19537Q3T 100 V blocking NFET + BSS138 fast gate pulldown → TPS26630 60 V eFuse → LM5176 four-switch buck-boost → ceramic/polymer output buffer (CONVERTER_4V15) → LTC4359 + DMN3008SFG ideal diode → TP3 BMS cell+ (BMS_CELL_PLUS). A TLV3012 threshold detector drives a normally-off AONS66614 and ten-resistor pulse dump bank on the BMS side.TP2 and TP4 remain the common high-current ground return.
Power Budget and Source Capability
The 4.15 V × 5 A target is 20.75 W. At 90% efficiency it requires about 23.1 W input.
Table
| Input condition | Hardware input limit | Assumed efficiency | Sustainable 4.15 V output (power/current) | Interpretation |
|---|---|---|---|---|
| 4.5 V worst case | 2.77 A nominal | 88% | 10.97 W / 2.64 A | Source/current-limit constrained |
| 5 V | 2.77 A nominal | 88% | 12.19 W / 2.94 A | Board limit; a 5 V/3 A contract itself is only 15 W and cannot provide 5 A output |
| 5 V/3 A theoretical contract maximum | 3.00 A | 88% | 13.2 W / 3.18 A | Absolute source-power ceiling, not full-performance operation |
| 9 V | 2.77 A nominal | 92% | 22.94 W / 5.53 A theoretical | Enough input power for the 5 A target, subject to the actual PD contract and converter limits |
| 15/20/21 V | 2.77 A nominal | 92% | More than 20.75 W available | Output is intentionally limited by the 5 A design target and converter/thermal capability |
Explicit limitation: full 4.15 V/5 A output is impossible from 5 V/3 A. It requires a higher-voltage contract, with 9 V at roughly 2.51 A minimum for 20.75 W output at 92% efficiency. A 30 W PD/PPS source remains recommended.
Source-Contract Constraint
This board cannot read CC pins or PD messages. It cannot know whether a given higher-voltage contract permits 2 A, 3 A, or another current. The TPS26630 current limit is therefore set to a conservative USB-C ceiling: RILIM=6.49 kΩ gives 2.77 A nominal and approximately 2.995 A at +8% tolerance. This avoids intentionally setting a hardware limit above 3 A, but does not prove that every source contract allows 2.77 A. The Pixel/adapter contract must be verified externally; operation with lower-current PDOs can still cause source shutdown or voltage collapse.
Coordinated Input Protection
- D1 SMBJ24A: 24 V working standoff; 26.7–29.5 V breakdown; 38.9 V maximum clamp at 16 A (datasheet pulse condition). It safely tolerates 21 V continuous.
- U1 TPS26630: 4.5–60 V recommended operation, 67 V absolute maximum; fixed 1× active current limiting (no intentional 2× pulse-current mode); reverse-current comparator support.
- Q1 CSD19537Q3T: 100 V blocking NFET, selected from TI's TPS2663x application guidance; substantial margin above the 38.9 V TVS clamp.
- Q6 BSS138: required low-capacitance fast gate-pulldown NFET driven by U1 DRV.
- LM5176 and AONS66614 bridge MOSFETs: 60 V absolute/VDS ratings, compatible with the 38.9 V rated TVS clamp.
- Divider R2=715 kΩ, R3=210 kΩ, R4=49.9 kΩ sets approximately 4.50 V UVLO and 23.45 V OVP nominal.
- C2=10 nF controls eFuse output slew; MODE is grounded for auto-retry; PGTH is grounded because PGOOD is unused.
Converter Settings Retained
- LM5176 at 300 kHz; 4.15 V nominal feedback; hiccup enabled.
- 12 mΩ common low-side PWM current shunt; optional average-current loop disabled.
- 2.2 µH XAL7030-222MEC power inductor.
- 100 nF BOOT-to-SW capacitors and Schottky charging diodes.
- Compensation and exact polymer output capacitors remain provisional pending final effective C/ESR and Bode/load-step validation.
Physical/Validation Risks Still Open
- The TVS clamp statement is valid at the cited datasheet waveform/current. Real internal cable inductance and surge current must be measured; repetitive or higher-energy surges require requalification.
- The 60 V LM5176 and 60 V bridge MOSFETs have margin to the 38.9 V nominal maximum clamp but layout overshoot must remain below 60 V; local ceramic damping and short input loops are mandatory.
- Exact C22–C25 polymer MPN, ESR, ripple rating, footprint, and ≤5 mm installed height remain unresolved.
- Compensation values remain provisional.
- Pixel/BMS behavior without a lithium cell and system thermals remain unverified.
- Phone/BMS attempted-charge current magnitude and duration are unverified. The 2.2 Ohm switched dump is sized for approximately 2 A / 9 W short events, not sustained charging. Prototype tests must establish the real profile before release.
- The nominal BMS-side clamp threshold is approximately 4.48 V with an estimated tolerance/offset band of roughly 4.3-4.65 V. Production release requires measured trip/reset limits and confirmation against the retained Pixel 7 BMS charge thresholds.
Acceptance Criteria Before Layout Release
- ERC/connectivity clean for the revised protection path.
- Bench sweep at 4.5/5/9/15/20/21 V and source-current-limited testing.
- Verify eFuse 2.77 A nominal limit, auto-retry, OVP/UVLO, hot-short, inrush, and reverse-current response.
- Capture D1/U1/Q1 and LM5176 VIN/SW waveforms during hot-plug, PD transitions, overload, and cable disconnect; confirm all remain below absolute maxima.
- Validate 5 A output only on a higher-voltage PD contract with adequate current and thermal margin.
- Finalize low-profile capacitors and compensation, then perform Bode/load-step and thermal testing.
- Verify Q7 orientation and zero-voltage startup: source on CONVERTER_4V15, drain on BMS_CELL_PLUS, body diode forward only toward the BMS.
- Force attempted charge-back at TP3 and verify U3 blocks reverse current from Q4/C16-C25 while U4/Q8 gives a bounded BMS-side response. Characterize dump pulse duration and temperature; do not assume sustained charge-current capability.
Project Overview
Preserved Interfaces and Mechanical Envelope
Regulated Output Requirement
Revised Architecture
Power Budget and Source Capability
Source-Contract Constraint
Coordinated Input Protection
Converter Settings Retained
Physical/Validation Risks Still Open
Acceptance Criteria Before Layout Release
