Schematic Build Update
Thought for 12 sec
I’ll replace the provisional display block with the verified ER-TFT028A3-4 8-bit I80 circuit, create/import the exact IMU part, recalculate charging and power rails, rebuild the GPIO map, then run pin-by-pin and ERC verification. PCB placement and routing will remain untouched.
Worked for 13 mins 12 sec
The verified display interface, 2.8 V translation, charger limits, and GPIO remap are in place. Two hardware items remain blocked by missing authoritative geometry/electrical data—the IMU footprint and backlight LED string—so I’m independently checking the completed schematic and documentation before closing.
Worked for 2 mins 55 sec
Implemented the verified ER-TFT028A3-4 50-pin display interface, 2.8 V supply and level translation, 8-bit I80 GPIO mapping, and safe BQ24074 500 mA/349 mA charging configuration. Final ERC, passive, and schematic-readability checks are clean; no PCB layout work was performed.
Remaining blockers
- LSM6DS3TR-C: authoritative LGA-14 land-pattern geometry was not accessible, so no footprint was guessed.
- Backlight driver: the panel documentation does not provide sufficient LED string forward-voltage/topology data;
BL_PWMis reserved but the power stage remains intentionally incomplete. - Future USB-C advertised-current detection remains unpopulated; this revision is safely locked to 500 mA.
Updated files: Project Specification, Block Diagram, Firmware Getting Started, and Board Bring-Up Plan.
Resolve remaining blockers
Review power budget
Prepare PCB placement
Inspect display interface
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Project Specification
Project Overview
Stage-1 schematic revision for the Companion Cube Mainboard. Status: Draft / blocked from schematic sign-off pending exact IMU CAD and a verified low-voltage 70 mA backlight circuit.
Current architecture
- USB-C sink/device with independent 5.1 kΩ CC1/CC2 Rd and native ESP32-S3 USB on GPIO19/20.
- BQ24074 PowerPath charger: OUT=
VSYS;VSYSfeeds TPS63020 3V3 buck-boost. - Exact raw EastRising ER-TFT028A3-4 no-touch panel represented as DS1 and mated through EastRising ER-CON50HT-1, 50-position 0.50 mm top-contact ZIF J3.
- Display logic: TLV70028DDCR fixed 2.8 V LDO (
DISP_2V8) and SN74AXC8T245 + SN74AXC4T245 fixed-direction 3V3→2V8 translation. - Shared 3V3 I2C remains on GPIO8/9 with one 4.7 kΩ pull-up pair.
Display electrical configuration
ER-TFT028A3-4 manufacturer datasheet: https://www.buydisplay.com/download/manual/ER-TFT028A3-4_Datasheet.pdf
- 8-bit 8080 Interface I: IM3=0, IM2=0, IM1=0, IM0=0 using four 10 kΩ pull-downs.
- Active data pins are FPC 25–32 (DB7..DB0). Pins 15–24 (DB17..DB8), RGB timing pins, SDO/SDI, TE, and no-touch X/Y pins are carried pin-for-pin through J3 but intentionally unused.
- RD (FPC35) is held inactive high to DISP_2V8 with 10 kΩ; design is write-only ESP-IDF I80.
- FPC36=WR, FPC37=DC/RS, FPC38=CS, FPC10=RESET.
- FPC40/41 VDDI and FPC42 VCI use regulated 2.8 V. Local 100 nF + 4.7 µF bypass is provided.
- TLV70028 is rated 200 mA; panel logic maximum is listed as 15 mA excluding backlight, leaving substantial margin for translators.
- Backlight blocker: manufacturer data confirms about 70 mA and one LEDK/four LEDA pins, but the current production datasheet/indexed manufacturer page did not provide a sufficiently authoritative LED forward-voltage/topology value. No GPIO-current or guessed resistor circuit was added. BL_PWM and the LED pins remain available, but the backlight power stage is incomplete.
Final ESP32-S3 GPIO allocation
Table
| GPIO | Function |
|---|---|
| 0 | BOOT only |
| 1 | RTC_INT_N |
| 2 | FUEL_ALERT_N |
| 4 | reserved for IMU INT1 (blocked pending exact IMU part) |
| 5 | reserved for IMU INT2 (blocked pending exact IMU part) |
| 6 | HAPTIC_EN |
| 7 | BL_PWM control/test point (driver blocked) |
| 8 | I2C_SDA |
| 9 | I2C_SCL |
| 10..17 | LCD D0..D7 |
| 18 | LCD_WR |
| 19 | native USB D− |
| 20 | native USB D+ |
| 21 | LCD_DC/RS |
| 43 | CHG_STAT_N |
| 44 | USB_PGOOD_N |
| 47 | LCD_CS |
| 48 | LCD_RESET |
| EN | reset/enable RC and button |
GPIO3/45/46 are unused. GPIO35–42 are not used because the N8R8 module reserves Octal flash/PSRAM resources. UART test access is intentionally omitted because the required interface/status set consumes the safe GPIO budget; USB Serial/JTAG remains available.
BQ24074 programming and NTC
Official TI Rev. N datasheet: https://www.ti.com/lit/ds/symlink/bq24074.pdf
- Hard mode: EN2=0, EN1=1 → USB500, maximum input current 500 mA. No GPIO or population option can select the higher programmable-adapter mode.
- ILIM safety resistor:
IIN_MAX = KILIM/RILIM; typ.KILIM=1550 AΩ; RILIM=3.09 kΩ gives 502 mA if adapter mode were ever entered. - Fast charge:
ICHG = KISET/RISET; typ.KISET=890 AΩ; RISET=2.55 kΩ gives 349 mA nominal (factor tolerance gives approximately 313–382 mA using 797–975 AΩ limits). - Input-current priority is preserved: actual charge current is limited to available input current minus OUT/system load; BQ24074 DPPM and thermal regulation reduce charge current before sacrificing system power.
- TS is not disabled. J5 provides a two-wire interface for a protected LiPo pack’s 10 kΩ NTC to TS and GND. TI thresholds are nominally 0.3 V hot and 2.1 V cold with 75 µA bias; a Vishay Type-2 / 10 kΩ NTC gives approximately 0–50 °C charging window. Battery pack must include the specified thermistor.
- CHG and PGOOD are open-drain and use existing 100 kΩ pull-ups to 3V3, read on GPIO43/44.
- Future USB-C advertised-current detection remains a future revision; no controller was added and no higher-current mode is enabled.
Power budget
Table
| Rail/load | Typical | Peak/design |
|---|---|---|
| 3V3 ESP32-S3 | 100–240 mA | 500 mA transient |
| 3V3 peripherals + translators | ~20 mA | 50 mA |
| 3V3 haptic driver/actuator allowance | ~80 mA | 120 mA |
| DISP_2V8 panel logic + translators | ~15–25 mA | 40 mA |
| Backlight | 70 mA | 70 mA (driver incomplete) |
| Total converted load | ~285–435 mA | ~780 mA equivalent planning case |
At 3.0 V minimum battery/system input and 85% TPS63020 efficiency, a 3.3 V × 0.78 A output case reflects about 1.01 A at VSYS. TPS63020 current capability is adequate in principle, but final thermal/inductor validation must include the selected haptic actuator and completed backlight stage. In USB mode the BQ24074 500 mA input limit cannot simultaneously support worst-case active load and 349 mA charging; DPPM therefore reduces or suspends charge current as intended. At light system load, nominal charging is ~349 mA. The TLV70028 worst-case dissipation from 3.3 V to 2.8 V at 40 mA is ~20 mW.
Verification status / blockers
- Completed: provisional 12-pin J3 and all provisional SPI nets removed; exact 50-pin panel symbol created from manufacturer pin table; exact ER-CON50HT-1 library connector used; 1:1 pin mapping and I80 logic wiring completed; regulated 2.8 V and level translation added; display/control test points added; BQ24074 set to USB500 and ~349 mA with active NTC interface; safe GPIO map recorded.
- Blocked: exact ST LSM6DS3TR-C is absent from Flux. ST confirms active LGA-14 2.5×3.0 mm and offers manufacturer CAD, but direct verified CAD/land-pattern geometry was not available through the accessible source. No substitute or guessed footprint was created.
- Blocked: backlight current stage pending authoritative LED forward-voltage/topology data or a manufacturer-qualified low-voltage driver/reference circuit.
- Optional advertised-current detector provisions were not added because no exact controller/interface was selected; the board remains safely fixed at USB500.
Change Notes
Removed provisional SPI display implementation; added exact 50-pin I80 panel interface, 2.8 V domain, translators, revised charger programming/NTC/status wiring, and a safe GPIO allocation. No PCB board, placement, routing, or layout operation was invoked.
Project Overview
Current architecture
Display electrical configuration
Final ESP32-S3 GPIO allocation
BQ24074 programming and NTC
Power budget
Verification status / blockers
Change Notes
