Schematic Build Update
Worked for 13 mins 12 sec
Created a thread, a component
ER-TFT028A3-4
EastRising/BuyDisplay raw 2.8-inch 240x320 IPS TFT LCD panel, ST7789V controller, no touch, 50-pin 0.50 mm FPC, parallel/RGB/serial interfaces, nominal 2.8 V VCI/VDDI and approximately 70 mA white LED backlight.
Verify ER-TFT028A3-4 symbol
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The verified display interface, 2.8 V translation, charger limits, and GPIO remap are in place. Two hardware items remain blocked by missing authoritative geometry/electrical data—the IMU footprint and backlight LED string—so I’m independently checking the completed schematic and documentation before closing.
Worked for 2 mins 55 sec
Implemented the verified ER-TFT028A3-4 50-pin display interface, 2.8 V supply and level translation, 8-bit I80 GPIO mapping, and safe BQ24074 500 mA/349 mA charging configuration. Final ERC, passive, and schematic-readability checks are clean; no PCB layout work was performed.
Remaining blockers
- LSM6DS3TR-C: authoritative LGA-14 land-pattern geometry was not accessible, so no footprint was guessed.
- Backlight driver: the panel documentation does not provide sufficient LED string forward-voltage/topology data;
BL_PWMis reserved but the power stage remains intentionally incomplete. - Future USB-C advertised-current detection remains unpopulated; this revision is safely locked to 500 mA.
Updated files: Project Specification, Block Diagram, Firmware Getting Started, and Board Bring-Up Plan.
Resolve remaining blockers
Review power budget
Prepare PCB placement
Inspect display interface
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Board Bring-Up Plan
- With battery and display disconnected, resistance-check USB_VBUS, VSYS, 3V3, DISP_2V8, and GND.
- Apply current-limited USB. Verify BQ24074 EN2=0/EN1=1 USB500 behavior, VSYS PowerPath operation, 3V3 regulation, then DISP_2V8=2.8 V ±2%.
- Confirm CHG_STAT_N and USB_PGOOD_N pull to valid 3V3 logic levels on GPIO43/44.
- Connect a protected LiPo with a verified 10 kΩ NTC on J5. Confirm charge is inhibited when NTC is absent/outside limits and resumes in the valid temperature window.
- Measure fast-charge current under light system load; target nominal is 890/2550 = 349 mA. Confirm charge current falls as system load approaches the 500 mA input limit.
- Verify ESP_EN, BOOT, and native USB enumeration on GPIO19/20.
- Scan I2C on GPIO8/9 and verify DRV2605L, MAX17048, RV-3028-C7, and VEML7700. Do not populate/claim LSM6DS3TR-C until exact manufacturer CAD/land pattern is imported.
- Without the panel attached, scope translator outputs: D0..D7, WR, DC, CS, RESET must swing 0–DISP_2V8, never 3V3. Confirm RD is held high and IM3..IM0 are all low.
- Inspect J3 top-contact orientation and independently continuity-check all 50 positions against the ER-TFT028A3-4 pin table before inserting the FPC.
- Attach panel with backlight unpowered. Initialize ST7789 over ESP-IDF I80 and verify color bars/read-independent writes.
- Backlight bring-up is blocked until a verified 70 mA current-limited driver is added. Never bridge LED pins to GPIO or an unverified resistor.
- Exercise haptic load and Wi-Fi transients while monitoring VSYS/3V3. In USB mode verify BQ24074 DPPM reduces charge current rather than collapsing system rails.
Pass criteria: no 3.3 V level reaches panel I/O, DISP_2V8 remains in tolerance, USB input remains limited to 500 mA, charge current is approximately 349 mA only when power/thermal headroom allows, and all implemented peripherals enumerate/respond.
