Schematic Build Update
Worked for 13 mins 12 sec
Created a thread, a component
ER-TFT028A3-4
EastRising/BuyDisplay raw 2.8-inch 240x320 IPS TFT LCD panel, ST7789V controller, no touch, 50-pin 0.50 mm FPC, parallel/RGB/serial interfaces, nominal 2.8 V VCI/VDDI and approximately 70 mA white LED backlight.
Verify ER-TFT028A3-4 symbol
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The verified display interface, 2.8 V translation, charger limits, and GPIO remap are in place. Two hardware items remain blocked by missing authoritative geometry/electrical data—the IMU footprint and backlight LED string—so I’m independently checking the completed schematic and documentation before closing.
Worked for 2 mins 55 sec
Implemented the verified ER-TFT028A3-4 50-pin display interface, 2.8 V supply and level translation, 8-bit I80 GPIO mapping, and safe BQ24074 500 mA/349 mA charging configuration. Final ERC, passive, and schematic-readability checks are clean; no PCB layout work was performed.
Remaining blockers
- LSM6DS3TR-C: authoritative LGA-14 land-pattern geometry was not accessible, so no footprint was guessed.
- Backlight driver: the panel documentation does not provide sufficient LED string forward-voltage/topology data;
BL_PWMis reserved but the power stage remains intentionally incomplete. - Future USB-C advertised-current detection remains unpopulated; this revision is safely locked to 500 mA.
Updated files: Project Specification, Block Diagram, Firmware Getting Started, and Board Bring-Up Plan.
Resolve remaining blockers
Review power budget
Prepare PCB placement
Inspect display interface
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Block Diagram
Text
USB-C J1 ├─ CC1/CC2 -> independent 5.1k Rd -> GND ├─ D-/D+ -> USBLC6-2 -> ESP32-S3 GPIO19/20 native USB └─ VBUS -> BQ24074 IN Protected 1-cell LiPo -> BQ24074 BAT Pack 10k NTC -> J5 -> BQ24074 TS (active) BQ24074 OUT/VSYS -> TPS63020 -> 3V3 ├─ ESP32-S3 + I2C peripherals/haptic └─ TLV70028 -> DISP_2V8 ESP32 GPIO10..17 -> SN74AXC8T245 -> LCD D0..D7 ESP32 GPIO18/21/47/48 -> SN74AXC4T245 -> WR/DC/CS/RESET DISP_2V8 -> ER-TFT028A3-4 VDDI/VCI ER-TFT028A3-4 <-> ER-CON50HT-1 J3, 50-pin 0.50mm top-contact ZIF BL_PWM GPIO7 -> test point; backlight current stage BLOCKED pending authoritative LED electrical data Shared I2C GPIO8/9 -> DRV2605L, MAX17048, RV-3028-C7, VEML7700 Reserved GPIO4/5 -> future exact LSM6DS3TR-C INT1/INT2 (part/CAD BLOCKED) Charger CHG/PGOOD -> GPIO43/44
No PCB/layout work is part of Stage 1.
