P-Channel MOSFET Circuit Design

Worked for 1 min 10 sec

I removed the blade fuse holder from the schematic and reconnected J1 PIN1 directly to the protected input net feeding the TVS and MOSFET source.

On the resettable fuse question: not recommended for your stated current profile. For a 24 V load with 6 A RMS and 15 A spikes, a PPTC/resettable fuse would need roughly ≥7–10 A hold current with enough trip margin to avoid nuisance trips. The available library searches did not find a suitable 24 V high-current PPTC, and high-current PPTCs add resistance, voltage drop, heat, and strong temperature derating.

Current state:

Fuse holder removed.
Single P-channel MOSFET protection remains.
TVS/ESD protection remains.
Input now goes directly to the protected input node.

Remaining work when execution can continue:

Update the project files to remove fuse-holder references.
Re-run schematic review.
If you still want resettable protection, select a specific high-current PPTC outside the current library or switch to an electronic fuse/load-switch approach.

treadlite

you didn't finish wiring all the connections

Worked for 12 sec

flux

You’re right — I’ll inspect the current nets, identify every floating or single-pin connection, then finish the schematic wiring and re-run review until the remaining issues are either fixed or clearly layout-only.

Worked for 2 mins 2 sec

flux

You were right — the schematic connectivity needed cleanup. I reconnected the full single-P-channel MOSFET protection circuit:

J1 PIN1 → VIN input rail → Q1 source, TVS cathode, input bulk cap, gate zener cathode, gate pull-up
Q1 drain → protected 24 V output → J2 PIN1 and output bulk cap
Q1 gate → zener anode, pulldown, pull-up
J1/J2 returns, TVS anode, bulk caps, and pulldown → GND
Renamed the stale fused input net to remove fuse-holder implication
Updated the design notes and bring-up plan to remove fuse-holder references

Current review result: schematic connectivity is complete; the remaining reported issues are PCB airwires, which are expected because the board has not been placed/routed yet.

Updated files:

I could not continue into layout/routing because execution credits ran out.

Run ERC again

Set board outline

Place power path

Check C2 rating

Files

Schematic

Layout

3D View

Capacitance

47uF

GND

Resistance

47kΩ

GND

Capacitance

47uF

Q1 D - J2 PIN1

J1 PIN1 - Q1 S

Q1 G - D2 A

Q1 D - J2 PIN1

J1 PIN1 - Q1 S

Q1 D - J2 PIN1

J1 PIN1 - Q1 S

Q1 G - D2 A

J1 PIN1 - Q1 S

Board Bring-Up Plan — 24V Protected Load Switch

Prerequisites

Current-limited bench supply capable of 24 V and at least the intended test current
Digital multimeter
Oscilloscope for transient/load-spike checks
Thermal camera or thermocouple for Q1 temperature checks
Initial current limit: 100 mA for no-load power-up, then increase gradually

1. Visual Inspection

Verify J1 and J2 terminal block orientation and pin markings.
Verify D1 SMBJ24A polarity: cathode to VIN_24V_RAW, anode to GND.
Verify D2 BZT52C12 polarity: cathode to VIN_24V_RAW/Q1 source, anode to MOSFET_GATE/Q1 gate.
Verify Q1 SUD19P06-60 orientation: source to VIN_24V_RAW, drain/tab to PROTECTED_24V, gate to MOSFET_GATE.
Inspect high-current copper around J1, Q1, and J2.

2. Power Rail Verification

Table

Rail	Source	Expected Voltage	Tolerance	Measure At	Current Limit	Pass Criteria
VIN_24V_RAW	J1 PIN1	24 V DC applied	Supply tolerance	J1 PIN1 to J1 PIN2 / D1 K to GND / Q1 S to GND	100 mA no-load first	No short; matches supply
MOSFET_GATE	R1/R2/D2/Q1 gate node	About 12 V below VIN_24V_RAW under normal input	Approximate zener clamp	Q1 G to Q1 S	100 mA no-load first	VGS magnitude stays below 20 V
PROTECTED_24V	Q1 drain/output	~24 V DC	MOSFET drop depends on load	J2 PIN1 to J2 PIN2	100 mA no-load first	Present only for correct polarity
GND	J1/J2 return	0 V reference	N/A	J1 PIN2 / J2 PIN2	Load dependent	Continuous low-resistance return

Procedure:

With no power applied, measure resistance from VIN_24V_RAW and PROTECTED_24V to GND. Confirm no short.
Apply 24 V at J1 with 100 mA current limit and no external load.
Confirm VIN_24V_RAW and PROTECTED_24V both read near 24 V.
Measure Q1 VGS and verify the zener clamp keeps it below ±20 V.
Reverse the input polarity at low current limit and verify PROTECTED_24V does not energize.

3. Load and Thermal Validation

Table

Test	Setup	Expected Result	Pass Criteria
Light load	24 V input, small resistive/electronic load	Output near input voltage	Stable output, no heating
6 A RMS load	24 V input, load set to 6 A	Q1 dissipates about 2.16 W worst-case using 60 mΩ	Q1 case temperature remains acceptable with final PCB copper
15 A transient	Short controlled pulse only	Momentary voltage drop and Q1 heating	No TVS overheating; no excessive output collapse for the allowed pulse duration
Reverse polarity	24 V reversed, current-limited	Q1 blocks output	J2 PIN1 remains unpowered

4. Connector and Interface Tests

Table

Connector	Pins to Verify	Test Method
J1 input	PIN1 = VIN_24V_RAW, PIN2 = GND	Continuity check to Q1 source / D1 cathode and GND
J2 output	PIN1 = PROTECTED_24V, PIN2 = GND	Continuity check to Q1 drain and GND

5. Expected Measurements Reference

Table

Measurement	Location	Expected Value	Instrument
Input voltage	J1 PIN1 to J1 PIN2	24 V nominal	DMM
Raw input rail	D1 K or Q1 S to GND	24 V nominal	DMM
Output voltage	J2 PIN1 to J2 PIN2	24 V nominal under light/no load	DMM
Q1 VGS	Q1 G to Q1 S	Approximately -12 V, never beyond ±20 V	DMM/Scope
Q1 temperature	Q1 package/tab region	Application dependent; verify margin	Thermal camera/thermocouple

Pass/Fail Summary

Table

Test Section	Result	Notes
Visual Inspection	[ ] Pass / [ ] Fail
Power Rails	[ ] Pass / [ ] Fail
Reverse Polarity	[ ] Pass / [ ] Fail
Load/Thermal	[ ] Pass / [ ] Fail
Connector Pinout	[ ] Pass / [ ] Fail

Board Status: [ ] Ready for load testing / [ ] Requires rework

Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Load and Thermal Validation
4. Connector and Interface Tests
5. Expected Measurements Reference
Pass/Fail Summary