Schematic Design Review

sudaraka

sudaraka

just remove the esp32 from the circuit and instead use a pin header.

flux

I’ll replace the ESP32-C3 module interface with a simple pin header while preserving the existing signals for an external controller connection, then verify the schematic connectivity.

flux

Done — I removed the ESP32-C3 module U4 and replaced it with J2, a 1x08 external-controller pin header.
J2 pinout:
  • Pin 1: 3V3
  • Pin 2: GND
  • Pin 3: SDA
  • Pin 4: SCL
  • Pin 5: ALT
  • Pin 6: ADR
  • Pin 7: DQ
  • Pin 8: GND
Verification passed: the new header nets are connected and ERC checks showed no open schematic issues. I also updated Concise BOM - Part Name, Value, Designators and Circuit and Documentation Reverification.
Fix issues and verify
Add ALRT pull-up
Make pull-ups populated
Update all documentation
Run full review
Explain header wiring
U1
C7 P2 - R6 P1
U2 VDD - R7 P1
J1 Signal - R3 P1
R14 P1 - U1 ADDR
R8 P2 - U1 SCL
J5 GND - R10 P1
J1 GND - C6 P1
R10 P2 - C14 P2
U1 A0 - C11 P1
U2 VINB+ - R2 P1
J5 GND - R10 P1
U4 GPIO4 - J4 P1
U2 VDD - R7 P1
SW1 2 - J6 Pin_3
J1 GND - C6 P1
U1 A2 - C14 P1
U2 VDD - R7 P1
U1 A1 - R6 P2
U4 GPIO4 - J4 P1
U4 GPIO10 - U1 ALRT
J5 GND - R10 P1
U2 VDD - R7 P1
U2 VINB+ - R2 P1
R14 P1 - U1 ADDR
U2 VDD - R7 P1
J5 GND - R10 P1
R12 P1 - J5 Signal
C13 P1 - R12 P2
J1 GND - C6 P1
U1 A0 - C11 P1
R14 P1 - U1 ADDR
U1 A2 - C14 P1
R4 P1 - U2 VINB-
R8 P2 - U1 SCL
U2 VINB+ - R2 P1
R4 P1 - U2 VINB-
U4 GPIO8 - R7 P2
C13 P1 - R12 P2
R10 P2 - C14 P2
SW1 2 - J6 Pin_3
U2 VDD - R7 P1
J1 Signal - R3 P1
USB5
C13 P1 - R12 P2
U1 A1 - R6 P2
C7 P2 - R6 P1
U1 A2 - C14 P1
U1 A0 - C11 P1
U3 VOUTB - R13 P1
R5 P1 - U2 VINA-
C7 P1 - U2 VINA+
U4 GPIO4 - J4 P1
U2 VDD - R7 P1
C7 P2 - R6 P1
U2 VDD - R7 P1
BAT
J1 GND - C6 P1
U4 GPIO8 - R7 P2
U3 VOUTA - R9 P1
U3 VOUTB - R13 P1
J5 GND - R10 P1
R10 P2 - C14 P2
U4 GPIO4 - J4 P1
C7 P1 - U2 VINA+
U2 VDD - R7 P1
U1 A2 - C14 P1
U2 VDD - R7 P1
U2 VDD - R7 P1
U1 A0 - C11 P1
U2 VDD - R7 P1
U2 VDD - R7 P1
U1 A1 - R6 P2
U4 GPIO10 - U1 ALRT
U2 VINB+ - R2 P1
R8 P2 - U1 SCL
C7 P1 - U2 VINA+
U1 A1 - R6 P2
U2 VINB+ - R2 P1
R12 P1 - J5 Signal
U3 VOUTA - R9 P1
R5 P1 - U2 VINA-
U4 GPIO8 - R7 P2
U2 VDD - R7 P1
R10 P2 - C14 P2
C4
Capacitance
1 µF
R12
Resistance
1000000 Ω
R3
Resistance
1000000 Ω
R11
Resistance
4700 Ω
C1
Capacitance
100 nF
C8
Capacitance
100 nF
R6
Resistance
1000 Ω
R5
Resistance
1000 Ω
R10
Resistance
1000 Ω
C2
Capacitance
100 nF
C10
Capacitance
100 nF
R9
Resistance
1000 Ω
C6
Capacitance
100 nF
R8
Resistance
10000 Ω
C11
Capacitance
100 nF
R14
Resistance
10000 Ω
C7
Capacitance
100 pF
C13
Capacitance
100 pF
R4
Resistance
1000 Ω
R13
Resistance
1000 Ω
R2
Resistance
100000 Ω
C16
Capacitance
100 nF
C14
Capacitance
100 nF
C12
Capacitance
100 nF
C9
Capacitance
100 nF
R1
Resistance
100000 Ω
C3
Capacitance
10 µF
C5
Capacitance
10 µF
C15
Capacitance
100 nF
R7
Resistance
10000 Ω
GND
GND
R14 P2 - J2 8
GND
J1
GND
GND
U3 VSS - C15 P2
GND
J3 Pin_3 - J4 P2
GND
C11 P2 - C12 P2
GND
J3
U3 VSS - C15 P2
J2
GND
GND
C11 P2 - C12 P2
GND
U2
U3 VSS - C15 P2
U3
J5
J3 Pin_3 - J4 P2
GND
R14 P2 - J2 8
J6
J4
SW1

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Schematic-Level Design Review
Date: 2026-07-10
Project: ESP32-C3 ADS1115 pH ORP Sensor Interface 4412
Scope
This review inspected the current schematic/netlist, component properties, and available ERC-style checks. It focuses on real schematic-level issues visible in the provided design. PCB routing airwires and generic missing-MPN manufacturing checks were not treated as schematic connectivity failures, except where part identity affects the electrical design.
Quick Status
  • ERC-style schematic checks returned no open errors/warnings for floating pins, power pins, no-connects, shorts, or undriven nets.
  • DRC airwires are present, but those are PCB routing/layout issues, not schematic-level faults.
  • The pH/ORP analog buffer topology is coherent in the netlist: MCP6002 follower outputs feed ADS1115 differential inputs through 1 kΩ isolation/filter resistors, and the biased BNC shield/reference nodes are not shorted to ground.
  • Decoupling/bulk capacitors are present for ADS1115/U1, MCP6002/U2, MCP6002/U3, and the 3V3 rail.
Confirmed Issues and Corrections
1. I2C is on ESP32-C3 boot-strapping pins
Observed schematic evidence
  • SCL connects U1:SCL, U4:GPIO9, and R8:P2.
  • SDA connects U1:SDA, U4:GPIO8, and R7:P2.
  • The ESP32-C3 Supermini datasheet indicates GPIO2, GPIO8, and GPIO9 are strapping pins; GPIO9 is the BOOT strap, and GPIO8 = 0 with GPIO9 = 0 is invalid. The same datasheet also identifies the onboard blue LED on GPIO8.
Why this is a real issue
The external I2C bus is electrically attached to boot-sampled pins. Any external device, pull state, bus fault, or the onboard GPIO8 LED load can affect reset/download behavior. GPIO9 should not be used as a normal I2C clock line in this design.
Actionable correction
Move I2C off GPIO8/GPIO9 to non-strap GPIOs. A practical reassignment in this schematic is:
  • SDA -> U4:GPIO6
  • SCL -> U4:GPIO7
Then reserve GPIO9 for BOOT behavior and avoid using GPIO8 for a shared external bus.
2. I2C pull-ups are not guaranteed to be populated
Observed schematic evidence
  • R7 and R8 are the SDA/SCL pull-ups to 3V3.
  • Both are 10 kΩ and have Exclude from BOM: true.
  • U1 is described as an ADS1115 module, but its exact module identity and onboard pull-ups are not controlled by an exact MPN/datasheet in the schematic.
  • TI ADS1115 documentation states SDA/SCL require pull-up resistors because I2C uses open-drain drivers.
Why this is a real issue
As drawn for assembly, the baseboard does not guarantee fitted I2C pull-ups. If the exact ADS1115 module variant is not controlled, relying on “likely onboard 103 pull-ups” is not enough for a schematic-level handoff.
Actionable correction
Choose one controlled approach:
  1. Populate the baseboard pull-ups and include R7/R8 in the BOM, typically 4.7 kΩ to 10 kΩ depending on bus length/capacitance and clock speed; or
  2. Specify an exact ADS1115 breakout/module with documented onboard I2C pull-ups and keep R7/R8 as clearly marked DNP alternatives.
Do not populate duplicate pull-ups without checking the final parallel resistance.
3. ADS1115 ALRT/RDY is connected to the MCU without a schematic pull-up
Observed schematic evidence
  • ALT connects only U1:ALRT and U4:GPIO10.
  • There is no resistor from ALT to 3V3 in the schematic.
  • TI ADS1115 documentation identifies ALERT/RDY as open-drain and recommends a pull-up to VDD when used.
Why this is a real issue
An open-drain alert/ready output cannot drive a defined logic-high level without a pull-up. An ESP32 internal pull-up could be enabled in firmware, but that is not guaranteed by the schematic.
Actionable correction
  • If ALRT/RDY is used: add a 4.7 kΩ to 10 kΩ pull-up from ALT to 3V3.
  • If it is not used: disconnect it from U4:GPIO10 and mark it intentionally unused, or explicitly annotate that firmware must enable an internal pull-up.
4. U1 is not defined as an exact controlled ADS1115 implementation
Observed schematic evidence
  • U1 part name: ADS1115 Module.
  • U1 MPN property: ADS111X, which is a family reference, not an exact purchasable part.
  • U1 package/case property: 10-VSSOP, which describes the bare IC package rather than a breakout-module footprint.
  • The datasheet tool found no datasheet URL for U1.
  • Schematic role details rely on likely onboard pull-ups from a photo, but the exact module circuit is not captured.
Why this is a real issue
The schematic mixes “module” assumptions with bare-IC package metadata. This affects whether onboard pull-ups exist, what the physical pinout/footprint is, and what support circuitry is truly present.
Actionable correction
Pick one implementation path:
  1. Replace/specify U1 as an exact ADS1115 breakout module with verified header pinout, footprint, onboard pull-ups, and MPN; or
  2. Treat U1 as the bare ADS1115 IC and explicitly include all required external support circuitry and the correct IC footprint/package.
This decision also resolves whether R7/R8 should be fitted.
5. Power-entry intent is ambiguous: USB5 and BAT are singleton nets
Observed schematic evidence
  • USB5 connects only to J6:Pin_1.
  • BAT connects only to J6:Pin_2.
  • 3IN connects J6:Pin_3 to SW1:2.
  • 3V3 connects SW1:1 to the system rail, including U4:3V3, U1:VCC, U2:VDD, and U3:VDD.
  • No charger, battery-protection circuit, or regulator is present on the schematic.
Why this is a real issue
The board is powered only if an external module provides a regulated 3.3 V rail into J6:Pin_3. USB5 and BAT are not part of any onboard power path as drawn.
Actionable correction
  • If J6 is intentionally an external power-module interface: annotate J6 clearly as “external charger/regulator module; Pin 3 must be regulated 3.3 V output” and keep USB5/BAT as external-only/pass-through nets.
  • If this board is intended to be standalone battery-powered: add the missing charger/protection/regulator power path and do not connect USB5 or BAT directly to 3V3.
6. ESP32-C3 Supermini power pin usage should be explicitly controlled
Observed schematic evidence
  • U4 is powered from the 3V3 net through U4:3V3; U4:5V is not connected.
  • The ESP32-C3 Supermini documentation says external power is applied to the 5V pin and GND, supporting 3.3 V to 6 V on that external input.
Why this is a real issue
The schematic bypasses the module’s documented 5V/external-input pin and feeds the 3V3 pin directly. That may be intentional if 3IN is a regulated 3.3 V rail, but the requirement is not explicitly stated in the schematic.
Actionable correction
Either:
  • Keep powering U4:3V3, but explicitly annotate 3IN/3V3 as a regulated 3.3 V rail and prohibit simultaneous USB/module power unless the module supports it; or
  • Power the module through its documented 5V input and use the module’s 3.3 V regulator/output only if the system current budget supports it.
7. BNC shell pins are electrically biased but named GND
Observed schematic evidence
  • J1/J5 shell pins are symbol pins named GND, but they connect to PHR and ORR, not to the schematic GND net.
  • Component role details state these BNC shell/mechanical pins are intentionally biased near 1.65 V, not grounded.
Why this is a real issue
The netlist is electrically coherent, but the pin name GND is misleading and can cause future edits or reviews to incorrectly tie the biased reference shields to true ground.
Actionable correction
Rename/annotate those connector pins as SHIELD, SHELL, or BIASED_SHIELD, and add a note near J1/J5: “BNC shell pins are biased reference nodes, not GND.”
Design Optimizations / Lower-Priority Cleanup
ADS1115 ADDR control
ADR connects U1:ADDR, R14 10 kΩ to GND, and U4:GPIO5. This is electrically valid and defaults to the ADS1115 GND address, but firmware can change the address if GPIO5 drives high. If the address does not need runtime control, simplify by tying ADDR directly to GND through the pull-down only and remove the MCU connection.
Manufacturing metadata
The checks report missing MPNs for generic passives and headers. This is not a schematic connectivity fault, but it must be resolved before fabrication/assembly procurement.
Items Reviewed With No Schematic-Level Fault Found
  • No external LEDs were found, so no missing LED current-limiting resistor issue was observed.
  • U1, U2, and U3 have local decoupling represented in the schematic; the 3V3 rail also has bulk capacitance.
  • The DS18B20 header path is coherent: J3:Pin_1 to 3V3, J3:Pin_2 to DQ, J3:Pin_3 to GND, and R11 4.7 kΩ from DQ to 3V3.
  • The pH and ORP buffer/filter paths are connected coherently in the inspected netlist.
  • The biased BNC shell/reference architecture is not shorted to ground in the schematic.
  1. Move I2C off GPIO8/GPIO9.
  2. Decide and document whether I2C pull-ups are on the baseboard or guaranteed by an exact ADS1115 module.
  3. Add or intentionally remove/annotate the ADS1115 ALRT/RDY pull-up path.
  4. Resolve U1 as either an exact module or a bare ADS1115 IC implementation.
  5. Clarify the J6 external power-module interface and U4 power-entry method.
  6. Rename/annotate BNC shell pins to prevent accidental grounding later.

  • Scope

  • Quick Status

  • Confirmed Issues and Corrections

  • 1. I2C is on ESP32-C3 boot-strapping pins

  • 2. I2C pull-ups are not guaranteed to be populated

  • 3. ADS1115 `ALRT/RDY` is connected to the MCU without a schematic pull-up

  • 4. U1 is not defined as an exact controlled ADS1115 implementation

  • 5. Power-entry intent is ambiguous: `USB5` and `BAT` are singleton nets

  • 6. ESP32-C3 Supermini power pin usage should be explicitly controlled

  • 7. BNC shell pins are electrically biased but named `GND`

  • Design Optimizations / Lower-Priority Cleanup

  • ADS1115 ADDR control

  • Manufacturing metadata

  • Items Reviewed With No Schematic-Level Fault Found

  • Recommended Fix Order

ESP32-C3 ADS1115 pH ORP Sensor Interface 4412

ESP32-C3 ADS1115 pH ORP Sensor Interface 4412 thumbnail
ESP32-C3 battery-powered pH and ORP probe interface using ADS1115 differential ADC, MCP6002 through-hole buffers, DS18B20 temperature compensation, and short net labels for firmware handoff.

Properties

Sensor

3.3

V

Arduino

I2C

Battery

Pricing & Availability

Distributor

Qty 1

Arrow

$8.74–$11.13

Digi-Key

$3.68

LCSC

$16.69–$17.39

Mouser

$11.45

TME

$6.21

Verical

$7.55–$15.85

Controls