Schematic and Documentation Reverification
Date: 2026-07-11
Project: ESP32-C3 ADS1115 pH ORP Sensor Interface 4412
Scope
This reverification checked the current schematic/netlist, automated ERC/passive/component-review checks, and the existing project files. Findings below are limited to issues observable in the current schematic or direct documentation mismatches.
Current Automated Check Status
The selected ERC/passive/component checks returned no open ERROR/WARNING/UNCERTAIN/OPEN items at the time of review. In particular, the automated checks did not flag floating pins, power-pin faults, shorts, undriven nets, missing decoupling, resistor power, capacitor voltage, pull-up/pull-down, or parts-available issues.
This does not clear design-intent issues that depend on ESP32-C3 boot behavior, exact module identity, or stale documentation.
Current Schematic Connectivity Observed
Main blocks
- U4 ESP32-C3 Supermini is powered from
3V3 on U4:3V3; U4:5V is not part of the active power net.
- U1 ADS1115 Module is powered from
3V3 and GND.
- U2 and U3 MCP6002-I/P op amps are powered from
3V3 and GND.
- J6 is an external power-module header:
USB5 only connects to J6 pin 1, BAT only connects to J6 pin 2, and 3IN connects J6 pin 3 to SW1 pin 2.
- SW1 connects the external
3IN rail to the board 3V3 rail through pins 2 and 1.
Digital/control nets
SDA: U1 SDA, U4 GPIO8, R7 P2.
SCL: U1 SCL, U4 GPIO9, R8 P2.
DQ: J3 pin 2, J4 P1, U4 GPIO4, R11 P2.
ADR: U1 ADDR, R14 P1, U4 GPIO5.
ALT: U1 ALRT, U4 GPIO10.
Analog nets
- pH path: J1 center
PHE -> R3 -> PHI -> U2A buffer -> PHB -> R5 -> PH+ -> U1 A0; biased reference PHR -> R6 -> PH- -> U1 A1.
- ORP path: J5 center
ORE -> R12 -> ORI -> U3A buffer -> ORB -> R9 -> OR+ -> U1 A2; biased reference ORR -> R10 -> OR- -> U1 A3.
VBD is formed by R1/R2 and filtered by C4; U2B and U3B buffer this bias into VBI and VBO.
Confirmed Schematic-Level Issues
1. I2C remains connected to ESP32-C3 boot/strap-sensitive pins
Observed current schematic:
SDA connects to U4:GPIO8.
SCL connects to U4:GPIO9.
The existing schematic review correctly identifies GPIO8/GPIO9 as ESP32-C3 boot/strapping-sensitive pins. This remains unchanged in the current schematic.
Actionable correction:
- Move I2C to non-strap pins on U4, such as GPIO6/GPIO7 if those are available in the selected ESP32-C3 Supermini pinout and not otherwise used.
- Update firmware pin definitions and all documentation after the schematic move.
2. Baseboard I2C pull-ups are optional/DNP, so I2C pull-ups are not guaranteed by the BOM
Observed current schematic:
- R7: 10 kΩ from
3V3 to SDA, Exclude from BOM: true.
- R8: 10 kΩ from
3V3 to SCL, Exclude from BOM: true.
- U1 is labeled
ADS1115 Module, but the exact module identity is not controlled by a real purchasable module MPN/datasheet in the schematic.
Actionable correction:
- Either include R7/R8 in the BOM as fitted pull-ups, or specify the exact ADS1115 module with documented onboard pull-ups.
- If both module pull-ups and baseboard pull-ups may be fitted, document the resulting parallel pull-up value and confirm it is acceptable for the bus.
3. ADS1115 ALRT/RDY is connected to GPIO10 but has no schematic pull-up
Observed current schematic:
ALT connects only U1 ALRT and U4 GPIO10.
- No resistor from
ALT to 3V3 is present.
Because the alert/ready pin is wired to the MCU, the schematic should define how it reaches a valid high state.
Actionable correction:
- Add a 4.7 kΩ to 10 kΩ pull-up from
ALT to 3V3, or explicitly mark ALT as firmware-internal-pull-up required.
- If ALERT/RDY will not be used, disconnect/NC it instead of routing it as an apparently usable signal.
4. U1 implementation is still ambiguous: module symbol but bare-family metadata
Observed current schematic:
- U1 part name:
ADS1115 Module.
- U1 MPN:
ADS111X, a family label rather than an exact part/module.
- U1 package/case:
10-VSSOP, which describes the bare IC package, not a typical header breakout module.
- U1 role details rely on likely onboard
103 pull-ups from a user photo.
Actionable correction:
- Choose and document one controlled implementation:
- exact ADS1115 breakout module with verified header pinout, onboard pull-ups, and footprint; or
- bare ADS1115 IC with correct IC footprint and all required external support circuitry included on this board.
5. Power entry remains external-module-dependent and should be clearer on the schematic
Observed current schematic:
USB5 and BAT are singleton nets at J6 pins 1 and 2.
- The active board rail enters through J6 pin 3 as
3IN, passes through SW1, then becomes 3V3.
- There is no onboard charger, battery protection, regulator, or power-path circuitry.
Actionable correction:
- If intentional, add a schematic note at J6: “External power module required; J6 pin 3 must be regulated 3.3 V.”
- If the board is meant to be standalone battery-powered, add the missing charger/protection/regulator circuitry.
6. ESP32-C3 Supermini is powered by its 3V3 pin, not the documented 5V input path
Observed current schematic:
- U4
3V3 is connected to the board 3V3 rail.
- U4
5V is not connected.
This can be valid only if the external rail is a regulated 3.3 V rail and the module supports direct 3V3-pin powering in the intended usage.
Actionable correction:
- Add a note that the board must be powered only from regulated 3.3 V when U4 is populated this way.
- Avoid simultaneous USB/module power unless the module power architecture is confirmed safe for backfeed conditions.
7. BNC shell pins are named GND in the connector symbols while intentionally biased above ground
Observed current schematic:
- J1 shell/mechanical pins are symbol pins named
GND but connect to PHR, not the schematic GND net.
- J5 shell/mechanical pins are symbol pins named
GND but connect to ORR, not the schematic GND net.
- The component role notes correctly say these pins are biased reference nodes, not ground.
Actionable correction:
- Rename/annotate connector pins as
SHIELD, SHELL, or BIASED_SHIELD if the part can be edited.
- Place a visible schematic note near J1/J5: “BNC shell/reference pins are biased nodes, not system GND.”
Items Verified as Coherent in the Current Schematic
- The pH and ORP differential ADS1115 channel mapping is coherent: pH uses A0-A1, ORP uses A2-A3.
- U2A/U3A are configured as voltage followers for the probe center inputs.
- U2B/U3B are configured as voltage followers for the mid-supply bias node.
- DS18B20 header J3 is coherent: pin 1
3V3, pin 2 DQ, pin 3 GND; R11 pulls DQ to 3V3.
- Local decoupling/bulk capacitors are represented for U1, U2, U3, and the rail/bias nodes.
- No LED components were found, so no missing LED current-limit resistor issue is present in the current schematic.
Documentation Reverification Findings
Firmware Starter - ESP32-C3 pH/ORP ADS1115
This file mostly matches the current schematic for SDA, SCL, and DQ, but has two direct mismatches:
- It says
ALT is optional but does not identify the current schematic connection to U4 GPIO10.
- It says
ADR is none/pulled low only, but the current schematic connects ADR to U4 GPIO5 as well as R14.
It also preserves the current GPIO8/GPIO9 I2C assignment, which matches the schematic but conflicts with the confirmed schematic review recommendation to move I2C off strap-sensitive pins.
ESP32-C3 ADS1115 pH/ORP Sensor Validation and Firmware Handoff Report
This file is partly current but has stale references:
- It describes the ESP32-C3 header as J2; the current schematic uses U4 for the ESP32-C3 Supermini and does not show J2 as the active MCU header.
- It maps
ALT and ADR as optional header-style signals, but the current schematic connects ALT to U4 GPIO10 and ADR to U4 GPIO5.
- It recommends/records GPIO8/GPIO9 I2C and treats that as acceptable if not forced low, while the later schematic review flags this as an issue to correct.
ADS1115 pH Sensor Design Notes
This file is substantially stale relative to the current schematic:
- It describes an Arduino/5 V design, but the current schematic is ESP32-C3/3.3 V.
- It says J3 pin 1 and R11 pull-up use
VCC_5V; the current schematic uses 3V3.
- It describes ADS1115 A2/A3 as auxiliary channels; the current schematic uses A2/A3 for ORP differential measurement.
- It describes J2 Arduino/header pin maps and
VCC_5V/I2C_SDA/I2C_SCL style nets, while the current schematic uses U4 and short nets 3V3, SDA, SCL, etc.
Actionable correction: mark this file as historical/obsolete or update it to the current ESP32-C3 + ORP design.
ESP32 and Arduino Uno Datasheet Summary
This file is general background and not fully current project documentation:
- It compares Arduino Uno, classic ESP32-WROOM-32, and ESP32 DevKit usage rather than the current ESP32-C3 Supermini design.
- It contains many 5 V Arduino and classic ESP32 pin recommendations that should not be treated as the current wiring map.
Actionable correction: keep it only as background, or add a top note saying it is not the authoritative current project pinout.
Schematic-Level Design Review
This file remains aligned with the current schematic. The same main issues are still present: GPIO8/GPIO9 I2C, optional/DNP I2C pull-ups, no ALT pull-up, ambiguous U1 identity, external-module-dependent power path, direct U4 3V3 powering, and misleading BNC shell pin names.
Recommended Fix Order
- Move I2C from U4 GPIO8/GPIO9 to safer ESP32-C3 GPIOs and update firmware/docs.
- Decide whether R7/R8 are fitted baseboard pull-ups or the exact ADS1115 module provides guaranteed onboard pull-ups.
- Add/annotate the
ALT pull-up or remove the ALT MCU connection if unused.
- Replace or fully specify U1 as either an exact ADS1115 module or a bare ADS1115 IC implementation.
- Add explicit schematic notes for J6 power requirements and U4 direct-3V3 powering.
- Rename/annotate biased BNC shell pins.
- Update the firmware and handoff files so they no longer conflict with the current schematic.