PCB Layout Guidance

flux

0:00

Work completed
  • Added project property Upstream_Keepout_Boundaries: “0.5 mm keepout margin around x16 upstream PCIe lane routing area”
  • Added project property Downstream_Keepout_Boundaries: “0.5 mm keepout margin around x8 downstream fan-out routing area”
Tasks not executed
  • Fetching actual keepout boundary coordinates from the PCB layout tool
  • Placing GND stitching vias at 5 mm pitch along both keepout boundaries
  • Assigning PCIe lane nets to the PCIE_Lanes_NetClass
  • Assigning SRNS_REFCLK nets to the SRNS_REFCLK_NetClass
  • Running Auto-Layout routing for PCIe lanes and SRNS_REFCLK nets
  • Performing ERC/DRC checks and summarizing compliance
Success criteria review
  • Upstream and downstream keepout boundaries recorded as properties: ✅
  • GND stitching vias placed at 5 mm pitch: ❌
  • PCIe and SRNS_REFCLK nets auto-routed under the correct net classes: ❌
  • ERC/DRC report confirming compliance: ❌
Recommended next step
Place the GND stitching vias along the defined keepout boundaries using the PCB layout tool, then verify they’re tied to GND and respect spacing rules before proceeding with net-class assignments and auto-routing.
183 days
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C11
Capacitance
Capacitance
J1 23 - U1 C3+
J1 12 - U1 B1-
J1 16 - U1 B3-
J1 18 - U1 C0-
C2 P1 - C10 P1
C14
Capacitance
Capacitance
J1 17 - U1 C0+
C4
Capacitance
Capacitance
C1
Capacitance
Capacitance
J1 22 - U1 C2-
C6
Capacitance
Capacitance
C3
Capacitance
Capacitance
J1 20 - U1 C1-
C1 P1 - C9 P1
C2
Capacitance
Capacitance
J1 21 - U1 C2+
C7
Capacitance
Capacitance
C12
Capacitance
Capacitance
C9
Capacitance
Capacitance
C1 P1 - C9 P1
C13
Capacitance
Capacitance
J1 13 - U1 B2+
C5
Capacitance
Capacitance
C10
Capacitance
Capacitance
C8
Capacitance
Capacitance
J1 19 - U1 C1+
J1 15 - U1 B3+
C2 P1 - C10 P1
J1 11 - U1 B1+
J1 10 - U1 B0-
J1 14 - U1 B2-
J1 24 - U1 C3-
J1 9 - U1 B0+
Hole3
Hole2
Hole1
Hole4
U2
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#4 AI Context Consensus Processor (ACCP)

#4 AI Context Consensus Processor (ACCP) thumbnail
PCIe Gen4 x16 Subsystem for ACCP 2U Blade: Integrated Switch, Lane Bifurcation, and SRNS Refclk with 85Ω Impedance Routing

Properties

Standard 10 Layer

No ERC or DRC issues detected

5 mm along the defined keepout boundaries

482.6

mm

PCIe 4.0

2025-10-29T00:00:00Z

Standard 4 Layer

20

ps

High Speed

Inner Layers 2 and 3

Upstream domain: 0.5 mm keepout margin around PCIe Gen4 x16 lane routing regions; Downstream domains: 0.5 mm keepout margin around x8 fanout regions; Stitching vias every 5 mm along differential pair return‐path boundaries.

0.5 mm keepout margin around x16 upstream PCIe lane routing area

85

Ω

0.5 mm keepout margin around x8 downstream fan-out routing area

88.9

mm

Top and Bottom

differential pair ~85 Ω, skew ≤2 ps, length matching ±50 mil, dedicated routing.

6

mil

target impedance: 85Ω; min spacing: 6 mil; max PN skew: 5 ps; max pair-to-pair skew: 20 ps; max vias per lane: 2

0.5 mm keepout around x8 downstream fan-out routing area

0.5 mm keepout around x16 upstream PCIe lane routing area

5

ps

``` mermaid graph TD CE["PCIe x16 Card-edge Connector"] -->|"16x PCIe Gen4 Lanes + SRNS REFCLK + Sideband + Power (12V, 3.3V_AUX)"| SW["PCIe Gen4 Switch (x16 Upstream)"] SW -->|"x8 PCIe Gen4 Lanes + Sidebands + Power"| EP1["Downstream x8 Endpoint Connector #1"] SW -->|"x8 PCIe Gen4 Lanes + Sidebands + Power"| EP2["Downstream x8 Endpoint Connector #2"] CE -.->|"Sideband: PERST#, CLKREQ#, WAKE#, SMBus/PD, Presence Detect"| SW CE -.->|"Power: 12V, 3.3V_AUX"| SW ```

enabled

2

target impedance: 85Ω; skew ≤ 2 ps; length matching ±50 mil; dedicated differential routing; max vias: 2

Pricing & Availability

Distributor

Qty 1

Controls