PCB Layout Guidance
Thought
Work completed
- Added project property Upstream_Keepout_Boundaries: “0.5 mm keepout margin around x16 upstream PCIe lane routing area”
- Added project property Downstream_Keepout_Boundaries: “0.5 mm keepout margin around x8 downstream fan-out routing area”
Tasks not executed
- Fetching actual keepout boundary coordinates from the PCB layout tool
- Placing GND stitching vias at 5 mm pitch along both keepout boundaries
- Assigning PCIe lane nets to the PCIE_Lanes_NetClass
- Assigning SRNS_REFCLK nets to the SRNS_REFCLK_NetClass
- Running Auto-Layout routing for PCIe lanes and SRNS_REFCLK nets
- Performing ERC/DRC checks and summarizing compliance
Success criteria review
- Upstream and downstream keepout boundaries recorded as properties: ✅
- GND stitching vias placed at 5 mm pitch: ❌
- PCIe and SRNS_REFCLK nets auto-routed under the correct net classes: ❌
- ERC/DRC report confirming compliance: ❌
Recommended next step
Place the GND stitching vias along the defined keepout boundaries using the PCB layout tool, then verify they’re tied to GND and respect spacing rules before proceeding with net-class assignments and auto-routing.
