Added project property Upstream_Keepout_Boundaries: “0.5 mm keepout margin around x16 upstream PCIe lane routing area”
Added project property Downstream_Keepout_Boundaries: “0.5 mm keepout margin around x8 downstream fan-out routing area”
Tasks not executed
Fetching actual keepout boundary coordinates from the PCB layout tool
Placing GND stitching vias at 5 mm pitch along both keepout boundaries
Assigning PCIe lane nets to the PCIE_Lanes_NetClass
Assigning SRNS_REFCLK nets to the SRNS_REFCLK_NetClass
Running Auto-Layout routing for PCIe lanes and SRNS_REFCLK nets
Performing ERC/DRC checks and summarizing compliance
Success criteria review
Upstream and downstream keepout boundaries recorded as properties: ✅
GND stitching vias placed at 5 mm pitch: ❌
PCIe and SRNS_REFCLK nets auto-routed under the correct net classes: ❌
ERC/DRC report confirming compliance: ❌
Recommended next step
Place the GND stitching vias along the defined keepout boundaries using the PCB layout tool, then verify they’re tied to GND and respect spacing rules before proceeding with net-class assignments and auto-routing.
Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power
PCIe Gen4 x16 Subsystem for ACCP 2U Blade: Integrated Switch, Lane Bifurcation, and SRNS Refclk with 85Ω Impedance Routing
Properties
Standard 10 Layer
No ERC or DRC issues detected
5 mm along the defined keepout boundaries
482.6
mm
PCIe 4.0
2025-10-29T00:00:00Z
Standard 4 Layer
20
ps
High Speed
Inner Layers 2 and 3
Upstream domain: 0.5 mm keepout margin around PCIe Gen4 x16 lane routing regions; Downstream domains: 0.5 mm keepout margin around x8 fanout regions; Stitching vias every 5 mm along differential pair return‐path boundaries.
0.5 mm keepout margin around x16 upstream PCIe lane routing area
85
Ω
0.5 mm keepout margin around x8 downstream fan-out routing area