Mini Retro TV Design
Worked for 40 mins 14 sec
The targeted manual routing pass created manufacturing-rule problems instead of converging cleanly, so I’m rolling those traces back to preserve the clean placement. I’ll leave the board placed and document routing as the remaining open item rather than leaving bad copper in the design.
continue please
Worked
Created a project doc
PCB Layout Notes — Mini Retro TV
Placement is complete on a compact 80 mm × 55 mm Standard 2 Layer board. Routing is not complete; an attempted manual routing pass was rolle...
Placed the 80 × 55 mm 2-layer PCB with the requested USB, display, Hall-row, battery, power, button, piezo, mounting-hole, and ESP32 antenna-edge priorities; details are in PCB Layout Notes.
Open item: routing is still pending — I rolled back the manual routing attempt because it created copper-rule violations, leaving the clean placed board with airwires instead of bad traces.
Suggested next steps: use a full-board routing pass from this placement, or approve a slightly larger board (e.g. 85 × 60 mm) if you want more routing margin before manufacturing.
Route and review
Run full routing
Try larger board
Fix routing issues
Check antenna keepout
Refine this doc
Ask about this doc
Schematic Notes — Mini Retro TV
Status
Schematic V1 is captured and ERC checks are clean for the selected review categories. Layout has not started yet.
Key Architecture Decisions
- ESP32-C3-MINI-1-N4 bare RF module is used instead of an ESP32 dev-board footprint.
- A dedicated XC6220B331MR 3.3 V LDO was added because ESP32-C3-MINI-1 requires 3.0–3.6 V on VDD33 and cannot be powered directly from a LiPo cell.
- MCP73831-2-OT charge current is set to about 200 mA using 5 kΩ on PROG.
- MCP73831 STAT drives a red charge LED and a green complete LED using the tri-state status behavior of the MCP73831 variant.
- Exactly 3x US1881 Hall latches are included as requested.
Important Caveats
- US1881 minimum supply is 3.5 V. They are powered from VSYS, so cassette detection is not guaranteed when the LiPo falls below about 3.5 V.
- MCP73831 has no power-path/load-sharing. Charging is most accurate when the slide switch is OFF and the system load is disconnected.
- Display header pinout is assumed: 1 VCC, 2 GND, 3 SCK, 4 MOSI, 5 CS, 6 DC, 7 RST, 8 BLK.
- Backlight assumes BLK is a low-side/cathode-style backlight control input that can be switched by Q1.
Power Nets
Table
| Net | Purpose |
|---|---|
| VBUS_RAW | USB-C VBUS before fuse |
| VBUS | Fused/protected USB 5 V to MCP73831 |
| BAT+ | LiPo positive and MCP73831 BAT |
| VSYS | Switched battery system rail after slide switch |
| 3V3 | Regulated logic rail from XC6220B331MR |
| GND | Common ground |
ESP32-C3 Pin Map
Table
| ESP32-C3 Pin | Net | Function |
|---|---|---|
| IO18 | USB_DN_MCU | USB D- |
| IO19 | USB_DP_MCU | USB D+ |
| IO4 | TFT_SCK | ST7789 SPI clock |
| IO6 | TFT_MOSI | ST7789 MOSI/SDA |
| IO7 | TFT_CS | ST7789 chip select |
| IO5 | TFT_DC | ST7789 data/command |
| IO10 | TFT_RST | ST7789 reset |
| TXD0 / GPIO21 | BL_PWM | Display backlight PWM gate drive |
| O0 / GPIO0 | HALL0 | Cassette ID bit 0 |
| IO3 | HALL1 | Cassette ID bit 1 |
| IO8 | HALL2 | Cassette ID bit 2; pulled high by Hall output pull-up |
| IO9 | BOOT_GPIO9 | Eject button and BOOT strap/test pad |
| RXD0 / GPIO20 | BUZZER_PWM | Passive piezo PWM drive |
| IO1 | BAT_ADC | Battery voltage ADC divider |
| IO2 | GPIO2_STRAP | Boot strap pull-up/test pad only |
| EN | EN | Enable/reset RC and test pad |
Selected Main BOM
Table
| Designator(s) | Part | Function |
|---|---|---|
| U3 | ESP32-C3-MINI-1-N4(4MB) | WiFi/BLE MCU module |
| U1 | MCP73831-2-OT | LiPo charger |
| U2 | XC6220B331MR | 3.3 V LDO |
| J1 | USB4215-03-A | USB-C receptacle |
| J2 | B2B-PH-K-S | JST-PH battery connector |
| J3 | 1x8 2.54 mm pin header | ST7789 display connector |
| U4-U6 | US1881ESE-AAA-000-RE | Hall latch sensors |
| Q1-Q2 | AO3400A | Backlight and buzzer low-side drivers |
| BZ1 | CPT-9019S-SMT-TR | Passive piezo transducer |
| D2 | USBLC6-2SC6 | USB data ESD protection |
| F1 | 0ZCJ0050FF2G | USB VBUS PTC fuse |
Next Layout Assumptions
- Board: rectangular 2-layer FR4.
- Place USB-C at an outer edge, display connector toward screen side, JST accessible, Hall sensors in a cassette-alignment row, ESP32 antenna at board edge with copper keepout.
- Add silkscreen labels for BAT, DISP, Hall0/1/2, Eject/BOOT, USB, charge LEDs, and revision.
Status
Key Architecture Decisions
Important Caveats
Power Nets
ESP32-C3 Pin Map
Selected Main BOM
Next Layout Assumptions
