Mini Retro TV Design
Worked for 40 mins 14 sec
The targeted manual routing pass created manufacturing-rule problems instead of converging cleanly, so I’m rolling those traces back to preserve the clean placement. I’ll leave the board placed and document routing as the remaining open item rather than leaving bad copper in the design.
continue please
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Created a project doc
PCB Layout Notes — Mini Retro TV
Placement is complete on a compact 80 mm × 55 mm Standard 2 Layer board. Routing is not complete; an attempted manual routing pass was rolle...
Placed the 80 × 55 mm 2-layer PCB with the requested USB, display, Hall-row, battery, power, button, piezo, mounting-hole, and ESP32 antenna-edge priorities; details are in PCB Layout Notes.
Open item: routing is still pending — I rolled back the manual routing attempt because it created copper-rule violations, leaving the clean placed board with airwires instead of bad traces.
Suggested next steps: use a full-board routing pass from this placement, or approve a slightly larger board (e.g. 85 × 60 mm) if you want more routing margin before manufacturing.
Route and review
Run full routing
Try larger board
Fix routing issues
Check antenna keepout
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PCB Layout Notes — Mini Retro TV
Status
Placement is complete on a compact 80 mm × 55 mm Standard 2 Layer board. Routing is not complete; an attempted manual routing pass was rolled back because it created copper-rule violations.
Board Setup
Table
| Item | Value |
|---|---|
| Board outline | Rectangular, 80 mm × 55 mm, 2 mm corner radius |
| Stackup | Standard 2 Layer |
| Assembly side | Top-side components only |
| Mounting | 4x M2 mounting holes in the corners |
| Current routing status | Unrouted airwires remain |
Placement Summary
- J1 USB-C is on the bottom/user-facing edge.
- U3 ESP32-C3-MINI-1 is on the right edge with antenna overhang/keepout intent.
- J3 display header is on the top/front edge.
- U4/U5/U6 Hall sensors are in a straight lower row with equal 10 mm pitch.
- J2 JST-PH battery connector is accessible on the left side and away from the antenna.
- Power block is grouped near the USB/battery region.
- SW2 Eject/BOOT is reachable from the top/front edge.
- BZ1 piezo is away from the ESP32 antenna area.
Current DRC / Open Items
- Airwires remain; the board is not ready for fabrication.
- No dangling-trace or overlapping-copper violations remain after rolling back the bad manual route attempt.
- U3 antenna/body is intentionally placed at the board edge/overhang region; review the final antenna keepout before manufacturing.
Final Pin Map
Table
| ESP32-C3 Pin | Net | Function |
|---|---|---|
| IO18 | USB_DN_MCU | USB D- |
| IO19 | USB_DP_MCU | USB D+ |
| IO4 | TFT_SCK | ST7789 SPI clock |
| IO6 | TFT_MOSI | ST7789 MOSI/SDA |
| IO7 | TFT_CS | ST7789 chip select |
| IO5 | TFT_DC | ST7789 data/command |
| IO10 | TFT_RST | ST7789 reset |
| TXD0 / GPIO21 | BL_PWM | Display backlight PWM |
| O0 / GPIO0 | HALL0 | Cassette ID bit 0 |
| IO3 | HALL1 | Cassette ID bit 1 |
| IO8 | HALL2 | Cassette ID bit 2 |
| IO9 | BOOT_GPIO9 | Eject button / BOOT strap |
| RXD0 / GPIO20 | BUZZER_PWM | Piezo PWM |
| IO1 | BAT_ADC | Battery voltage ADC |
| IO2 | GPIO2_STRAP | Boot strap/test pad only |
| EN | EN | Enable/reset RC and test pad |
JLCPCB Fab Notes Draft
- 2-layer FR4, 1.6 mm thickness.
- 1 oz copper is acceptable for this current class.
- HASL is acceptable for low cost; ENIG preferred for flatter pads and nicer small-batch finish.
- Solder mask: green or black; silkscreen white.
- Do not order fabrication until routing is completed and DRC is clean.
Recommended Next Action
Use a full-board autorouter/manual routing workflow from the placed state, or authorize a slightly larger board (for example 85 mm × 60 mm) if routing congestion appears around the USB/power section or ESP32/display bus.
Status
Board Setup
Placement Summary
Current DRC / Open Items
Final Pin Map
JLCPCB Fab Notes Draft
Recommended Next Action
