The current placement is arranged as a 90 mm × 60 mm left-to-right board, which matches the required USB-left/output-right flow better than the original portrait outline. I’m setting that as the working outline and restoring the intended 4-layer stackup.
Placement is now on a 90 × 60 mm 4-layer board with no open placement, footprint, overlap, layer, or ERC issues in the checked categories; the only remaining board errors are expected unrouted connections because I intentionally cleared stale routing after the schematic rewrite. I’m saving the structured change report now.
Implemented the approved hardware-only redesign: removed the MCU/programming architecture, added hardware timers/debounce/POR/logic/selectors, reworked the board to a 90 × 60 mm 4-layer left-to-right layout, and cleared stale routing. I updated the detailed report here: Hardware-Only Revision Change Log.
Open items:
Final routing is not done; remaining PCB errors are expected airwires because routing was intentionally cleared after the schematic rewrite.
HV/isolation, feedback values, dead-time/missing-clock behavior, logo asset, and sample-kit mechanical fit still require engineering review.
Suggested next steps:
Review the new placement and board size.
Approve final routing.
Run the separate HV safety, DFM, BOM, and prototype-readiness review before any manufacturing export.