Analog to Digital Converters - ADC Single-channel, 9-bit, 1.3-GSPS analog-to-digital converter (ADC) with JESD204C interface 144-FCBGA -40 to 85 ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltagecontrolled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. Features • ADC Core: – Resolution: 9 Bit – Maximum sampling rate: 1.3GSPS – Non-interleaved architecture – Internal dither reduces high-order harmonics • Performance specifications (–1dBFS): – SNR (100 MHz): 53.5dBFS – ENOB (100 MHz): 8.5 Bits – SFDR (100 MHz): 64dBc – Noise floor (–20dBFS): –143dBFS • Full-scale input voltage: 80 mVPP-DIFF • Full-power input bandwidth: 6GHz • JESD204C Serial data interface: – Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes – Maximum baud-rate: 17.16Gbps – 64B/66B and 8B/10B encoding modes – Subclass-1 support for deterministic latency – Compatible with JESD204B receivers • Optional internal sampling clock generation – Internal PLL and VCO (7.2–8.2GHz) • SYSREF Windowing eases synchronization • Four clock outputs simplify system clocking – Reference clocks for FPGA or adjacent ADC – Reference clock for SerDes transceivers • Timestamp input and output for pulsed systems • Power consumption (1GSPS): – Quad Channel: 450mW / channel – Dual channel: 625mW / channel – Single channel: 940mW • Power supplies: 1.1V, 1.9V #CommonPartsLibrary #IntegratedCircuit #ADC #HighSpeedADC #RFADC #JESD204C #13GSPS #9bitADC #DirectRFSampling #TexasInstruments #MixedSignal #DataAcquisition #JESD204

Octal Ultrasound AFE with Digital Demodulator, JESD204B #CommonPartsLibrary #IntegratedCircuit #data-acquisition #AFE

IC RF TxRx Only 300MHz ~ 6GHz 196-LFBGA, CSPBGA AD9371 is a highly integrated dual-channel RF transceiver covering 300 MHz to 6 GHz, with up to 100 MHz receiver bandwidth, 250 MHz transmit synthesis bandwidth, integrated synthesizers, and a JESD204B interface. Keywords: AD9371, dual RF transceiver, 300MHz–6GHz, JESD204B, wideband radio

14-Bit 1 GSPS High-Speed Pipeline Analog-to-Digital Converter (ADC) – High-performance ADC designed for software-defined radios (SDR), radar systems, communications equipment, satellite receivers, instrumentation, signal intelligence, wideband data acquisition, and high-speed embedded processing. The Analog Devices AD9690BCPZ-1000 provides 14-bit resolution with a maximum sampling rate of 1 GSPS, using a differential analog input and JESD204B serial digital output for high-speed connection to an FPGA or other high-performance digital processing device. It supports an approximately 2 GHz full-power analog input bandwidth, programmable differential input termination of 50 Ω, 100 Ω, 200 Ω, or 400 Ω, an integrated voltage reference, differential clock input, and flexible JESD204B lane configurations. At 1 GSPS, typical total power consumption is around 2 W. The device also includes two integrated wideband digital processing paths, including NCO and cascaded half-band filtering, which can reduce the amount of data that needs to be processed downstream. The AD9690BCPZ-1000 uses a 64-lead LFCSP package (9 × 9 mm), operates over −40°C to +85°C, and is listed by DigiKey as active. It is particularly well suited for systems where a high-speed ADC needs to interface directly with an FPGA through JESD204B, such as the AMD Kintex UltraScale+ FPGA you provided earlier.