Part Datasheet Review and Validation

flux

Completed the TC358768AXBG review and saved the full findings in Part Datasheet Review: TC358768AXBG. The project already had an official Toshiba datasheet URL set; MPN, package, 72-ball pinout, and 9×9 center-omitted VFBGA footprint check out.
Open items:
  • Pin Type is still Unspecified on all terminals.
  • Pin Description fields are not populated.
  • Footprint pad/mask/paste details should be confirmed against assembler/Toshiba land-pattern guidance before fab.
Suggested next steps:
  1. Populate Pin Type and Pin Description properties from the datasheet.
  2. Normalize the description to “RGB / parallel port to MIPI DSI display bridge, 72-ball 0.4 mm VFBGA.”
  3. Run a manufacturing-focused footprint/land-pattern review.
A

adrian95

Populate the Pin Type and Pin Description properties from the Toshiba datasheet.

flux

I’ll apply the Toshiba datasheet pin functions to all 72 terminals, then re-read the symbol to verify the Pin Type and Pin Description updates.

flux

I found the official functional signal list; I’m now updating every terminal with datasheet-derived electrical type and description.

flux

Populated Pin Type and Pin Description for all 72 TC358768AXBG terminals from the Toshiba functional signal list, including power, ground, parallel RGB input, MIPI DSI PHY, I2C/SPI, GPIO, reset, clock, and sync pins. Verified afterward that the updated properties are present across the symbol.
Open items:
  • None for this request.
Suggested next steps:
  1. Run ERC/property checks now that pin types are populated.
  2. Add Bus Group / differential-pair metadata for the MIPI DSI lanes.
  3. Do a manufacturing-focused review of the 0.4 mm VFBGA footprint.
Metadata and checks
Run ERC check
Add MIPI metadata
Review VFBGA footprint
Update review file
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Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
VSS_1
A1
Ground
Bottom
Ground reference (VSS).
PD17
A2
Input
Parallel port input data bit 17; configurable as GPIO4.
PD19
A3
Input
Parallel port input data bit 19; configurable as GPIO6.
PD21
A4
Input
Parallel port input data bit 21; configurable as GPIO8.
PD23
A5
Input
Parallel port input data bit 23; configurable as GPIO10.
GPIO2
A6
Bi-Directional
GPIO2 signal; optional SPI_MISO signal; 4 mA drive.
I2C_SCL
A7
Open Collector
Open-drain I2C serial clock or SPI_SCLK; 4 mA drive.
MSEL
A8
Input
Mode select input: 0 = test mode, 1 = normal mode.
VSS_2
A9
Ground
Bottom
Ground reference (VSS).
VDDC_1
B1
Power In
Top
1.2 V internal core supply input (VDDC).
PD16
B2
Input
Parallel port input data bit 16; configurable as GPIO3.
PD18
B3
Input
Parallel port input data bit 18; configurable as GPIO5.
PD20
B4
Input
Parallel port input data bit 20; configurable as GPIO7.
PD22
B5
Input
Parallel port input data bit 22; configurable as GPIO9.
GPIO1
B6
Bi-Directional
GPIO1 signal; optional SPI_SS or interrupt signal; 4 mA drive.
I2C_SDA
B7
Open Collector
Open-drain I2C serial data or SPI_MOSI; 4 mA drive.
RESX
B8
Input
System reset input, active low; Schmitt input.
VDDIO_1
B9
Power In
Top
I/O supply input, 1.8 V or 3.3 V VDDIO.
PD15
C1
Input
Parallel port input data bit 15.
PD14
C2
Input
Parallel port input data bit 14.
VSS_3
C3
Ground
Bottom
Ground reference (VSS).
VSS_4
C4
Ground
Bottom
Ground reference (VSS).
VSS_5
C5
Ground
Bottom
Ground reference (VSS).

TC358768AXBG