STPMIC25APQR Audit

adrian95

adrian95

Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.

flux

I’ll assign group-level Terminal Order with Power as 1 and Ground as 10, set Power Top/Ground Bottom, and split the remaining groups across Left/Right as evenly as possible despite only four orientation values being available.

flux

Done — I assigned Terminal Order and Orientation to all pins and verified the updates.
Open items:
  • There are only four Orientation values (Top, Bottom, Left, Right) but six groups, so unique orientation per group is not physically possible. I used: Power=Top, Ground=Bottom, Buck/I2C=Left, LDO/Control=Right.
Applied order:
  • Power: 1
  • Buck: 2
  • LDO: 3
  • I2C: 4
  • Control: 5
  • Ground: 10
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STPMIC25APQR Part Audit
Date: 2026-07-13
Source reviewed
  • Manufacturer: STMicroelectronics
  • Manufacturer part number: STPMIC25APQR
  • Official datasheet: https://www.st.com/resource/en/datasheet/stpmic25.pdf
  • Datasheet revision found: DS14278 Rev 6, February 2026
  • Part function: Highly integrated PMIC for microprocessor units / STM32MP2-family systems.
Existing project metadata check

Table

FieldProject valueDatasheet valueResult
MPNSTPMIC25APQRSTPMIC25APQRMatch
ManufacturerSTMicroelectronicsSTMicroelectronicsMatch
Datasheet URLhttps://www.st.com/resource/en/datasheet/stpmic25.pdfOfficial ST datasheet URLMatch; already set
DescriptionHighly integrated PMIC for microprocessor systems with bucks, LDOs, I2C/digital controlFully integrated PMIC for microprocessor unitsMatch
Part TypeProcessorPower management IC / PMICMismatch: should be Power Management, not Processor
Package / packingFootprint is QFN40P650X650X90-57N-DVQFN 56L, 6.5 x 6.5 x 0.9 mm, exposed padElectrically/mechanically consistent; filename is non-datasheet nomenclature
Pad count57 pads56 leads + exposed pad EPGNDMatch
Key datasheet specs
  • Input voltage range: VIN 2.8 V to 5.5 V; typical 3.6 V or 5 V.
  • VIO input voltage: 1.7 V to 3.6 V; typical 1.8 V or 3.3 V.
  • Ambient operating temperature: -40°C to +105°C.
  • Junction temperature specification range noted in datasheet conditions: -40°C to +125°C.
  • Switching regulators: 7 buck SMPS converters, 2 MHz switching frequency, adaptive COT topology, programmable currents.
  • LDOs: 6 adjustable general-purpose LDOs, 1 DDR termination LDO, 1 USB PHY LDO, and VREFDDR reference LDO.
  • Interfaces: I2C plus digital I/O control pins; PONKEYn, WAKEUPn, RSTn, INTn, PWRCTRL1/2/3.
  • Package mechanical data: VQFN 56L, D/E = 6.5 mm BSC, A = 0.80 to 0.90 mm, pitch e = 0.4 mm BSC, lead width b = 0.17 to 0.23 mm, exposed pad D2/E2 = 4.45 to 4.55 mm.
  • Absolute max highlights: VIN/BUCKxIN/VLXx/LDOxIN/PONKEYn/VBUS up to +6.5 V; VIO/SDA/SCL/RSTn/PWRCTRLx/INTn/WAKEUPn up to +4.2 V; INTLDO up to +2 V.
Symbol and pinout cross-check
All 56 perimeter pins map to the datasheet pin table by number and function. The exposed pad is present as pad/pin 57 and corresponds to datasheet EPGND/ePad.
Minor naming observations:
  • Active-low pins are represented with uppercase terminal names in the project (PONKEYN, WAKEUPN, RSTN, INTN), while the datasheet uses PONKEYn, WAKEUPn, RSTn, INTn. Function and pin number match.
  • The exposed pad terminal is named EP in the project, while the datasheet calls it EPGND / ePad. Function and pad number match; exact label could be renamed to EPGND for datasheet fidelity.
Footprint cross-check
The footprint has 56 perimeter pads plus a central exposed pad, matching the datasheet package concept. Perimeter pad pitch is 0.4 mm and pad width is 0.20 mm, consistent with the VQFN 56L mechanical data. The body/fab outline is 6.5 mm square and the exposed pad is 4.55 mm square, matching the datasheet maximum exposed-pad dimension.
Notes:
  • The footprint does not encode the ST application-note recommendation for exposed-pad thermal via array/paste segmentation. That is usually a board-layout implementation detail rather than a symbol/pinout mismatch.
  • ST AN6128 recommends thermal vias under the exposed pad: at least 9 vias, example 5 x 5 matrix, about 0.2 mm drill / 0.5 mm via pad, 0.7 mm spacing, and 50% to 75% solder-paste coverage on the exposed pad.
Functional pin groups applied
Each physical pin was assigned to exactly one primary functional group; no pin is duplicated across groups.

Table

GroupPinsCount
Main Power InputVIN, VBUS2
I/O SupplyVIO1
LDO InputsLDO12IN, LDO3IN, LDO56IN, LDO78IN4
Buck Power InputsBUCK1IN, BUCK2IN, BUCK3IN, BUCK4IN, BUCK5IN, BUCK6IN, BUCK7IN7
GroundsAGND, GNDLDO, PGND1, PGND2, PGND3, PGND4, PGND5, PGND6, PGND7, EP10
LDO OutputsLDO1OUT, LDO2OUT, LDO3OUT, LDO4OUT, LDO5OUT, LDO6OUT, LDO7OUT, LDO8OUT8
Internal RegulatorINTLDO1
DDR ReferenceVREFDDR1
Buck Feedback InputsVOUT1, VOUT2, VOUT3, VOUT4, VOUT5, VOUT6, VOUT77
Buck Switch NodesVLX1, VLX2, VLX3, VLX4, VLX5, VLX6, VLX77
I2C InterfaceSCL, SDA2
Power ControlPONKEYN, WAKEUPN, PWRCTRL1, PWRCTRL2, PWRCTRL35
Reset and InterruptRSTN, INTN2
Total57
Mismatches / recommendations
  1. Project Part Type mismatch: project property is Processor, but datasheet identifies STPMIC25APQR as a power management IC. Recommended value: Power Management.
  2. Exposed pad name mismatch: project terminal is EP; datasheet name is EPGND / ePad. Electrical function is correct; consider renaming the terminal to EPGND for exact datasheet naming.
  3. Active-low naming style: project uses uppercase N suffix while datasheet uses lowercase n. This is a style mismatch only; pin numbers/functions are correct.
  4. Layout implementation recommendation: for an actual PCB, implement ST's exposed-pad thermal-via and solder-paste guidance from AN6128.
Changes made
  • Added functional Pin Group and Section properties to all 57 terminals.
  • Updated Pin Type values from Unspecified to datasheet-based electrical roles.
  • Added datasheet-backed Pin Description text to every terminal.
  • No duplicate pin grouping was introduced; each terminal has exactly one functional group.

  • Source reviewed

  • Existing project metadata check

  • Key datasheet specs

  • Symbol and pinout cross-check

  • Footprint cross-check

  • Functional pin groups applied

  • Mismatches / recommendations

  • Changes made