Part Audit Review

flux

I’ll correct the pin name and ground types, add explicit UFQFPN48 package metadata, populate all 49 terminal descriptions from the ST pin table, then re-inspect the part to verify the changes.

flux

Corrected and verified:
  • Pin 47 renamed to VLXSMPS in both symbol and footprint.
  • Pins 48 and 49 changed to Ground.
  • UFQFPN48 package dimensions, pitch, and exposed-pad details added to project metadata.
  • Datasheet-based descriptions added to all 49 terminals.
  • Re-inspection confirms 49 pins remain present with correct numbering.
A

adrian95

Organize the terminals into proper pin groups, sections, orientations, and terminal order.

flux

I’ll reorganize the parametric symbol by functional section, assign every terminal a pin group and deterministic order, set conventional signal/power orientations, then inspect the rendered symbol for completeness.

flux

Organized and verified all 49 terminals:
  • Functional sections: GPIO, backup/low-speed, control/clock, sub-GHz radio, and power.
  • Pin groups assigned by port or function.
  • Conventional left/right/top/bottom orientations applied.
  • Deterministic, unique terminal ordering established within each group.
  • Pin numbers, names, types, descriptions, and footprint mappings remain intact.
Improve symbol readability
Fix paste aperture
Add symbol grouping
Review package footprint
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Files

Pins

Symbol

Layout

Preview

PB3
Pin Number
1
PB7
Pin Number
5
RFI_N
Pin Number
21
VSSSMPS
Pin Number
48
PA4
Pin Number
12
PA0
Pin Number
7
VDDPA
Pin Number
25
PC14-OSC32_IN
Pin Number
39
PA5
Pin Number
13
PB4
Pin Number
2
PA1
Pin Number
8
PA13
Pin Number
36
PA10
Pin Number
33
PA12
Pin Number
35
PB2
Pin Number
31
PB5
Pin Number
3
PA9
Pin Number
17
VDD
Pin Number
11
PA11
Pin Number
34
PA3
Pin Number
10
RFI_P
Pin Number
20
PC13
Pin Number
38
PB12
Pin Number
32
VFBSMPS
Pin Number
45
PA14
Pin Number
42
VDDRF
Pin Number
28
OSC_OUT
Pin Number
27
PA7
Pin Number
15
GND
Pin Number
49
VR_PA
Pin Number
24
PB8
Pin Number
6
NRST
Pin Number
18
VDDA
Pin Number
41
RFO_LP
Pin Number
22
VDDRF1V55
Pin Number
29
PA15
Pin Number
43
PA6
Pin Number
14
VBAT
Pin Number
37
OSC_IN
Pin Number
26
PB0-VDD_TCXO
Pin Number
30
PA2
Pin Number
9
VDD
Pin Number
44
VLXSMPS
Pin Number
47
PB6
Pin Number
4
RFO_HP
Pin Number
23
PC15-OSC32_OUT
Pin Number
40
VDDSMPS
Pin Number
46
PH3-BOOT0
Pin Number
19
PA8
Pin Number
16
Part Audit Report
Scope
Audit of the published Flux part STM32WLE5CCU6 against STMicroelectronics datasheet DS13105 Rev 12 (December 2022).
Official datasheet already attached: https://www.st.com/resource/en/datasheet/stm32wle5c8.pdf
Existing part information

Table

FieldCurrent valueAudit
Manufacturer part numberSTM32WLE5CCU6Correct
ManufacturerSTMicroelectronicsCorrect
Part typeIntegrated CircuitsBroad; “Microcontroller” or “RF Transceiver MCU” would be more specific
DescriptionSTM32WLE5CCU6 / UFQFPN48_STM variantsIncomplete as a functional description
Pin/pad count49Correct: 48 perimeter leads plus exposed pad 49
PackageNot set as a project property; description and footprint identify UFQFPN48Missing explicit package property
Datasheet URLST official PDFCorrect; no update required
Key verified specifications
  • 32-bit Arm Cortex-M4 MCU, up to 48 MHz.
  • 256 KB Flash and up to 64 KB SRAM for the CC density option.
  • Integrated sub-GHz radio supporting LoRa, (G)FSK, (G)MSK, and BPSK.
  • Radio frequency range 150–960 MHz.
  • Programmable RF output up to +22 dBm on the high-power output and +15 dBm on the low-power output.
  • Main operating supply range 1.8–3.6 V.
  • 6 temperature suffix: -40 to +85 °C ambient, up to 105 °C junction.
  • Package: UFQFPN48, 7 × 7 mm, 0.5 mm pitch, with exposed ground pad 49.
Datasheet locations: feature summary pp. 1–3; pin definition Table 20; operating conditions Table 26; UFQFPN48 package information and recommended footprint pp. 135–136; ordering information p. 142.
Symbol and pin-map cross-check
Correct
  • All package numbers 1–49 are present exactly once, including two separate VDD pins (11 and 44).
  • GPIO, RF, oscillator, reset, boot, and supply pin numbering matches the UFQFPN48 pin table.
  • RF pin directions are generally represented correctly: RFI_P/RFI_N as inputs and RFO_LP/RFO_HP as outputs.
Mismatches and omissions
  1. Pin 47 name is incorrect
    • Current: VLCSMPS
    • Datasheet: VLXSMPS
    • Severity: High, because the visible pin name is wrong and may propagate into schematics/net naming.
  2. Exposed pad 49 is named GND instead of the datasheet name VSS
    • Electrically understandable, but not an exact datasheet match.
    • Datasheet requires pad 49 to be connected to VSS.
  3. Ground-related electrical types are incorrect
    • Pad 49 GND and pin 48 VSSSMPS are set to Power Out.
    • They should be represented as Ground (or the platform-equivalent supply/ground type), not power outputs.
  4. Pin descriptions are missing for all 49 terminals
    • No Pin Description properties were found.
    • At minimum, supply-domain purpose, RF input/output role, oscillator role, BOOT0/reset behavior, and GPIO alternate-function summary should be populated.
  5. Supply pin type metadata is coarse
    • Supply-domain pins are represented as Power In, while the datasheet classifies them as supply pins (S). This is acceptable for positive supplies, but ground pins need correction as noted above.
  6. Symbol organization metadata is absent
    • Section, pin group, orientation, and terminal order properties are blank in the rendered pin table. The symbol is usable, but functional grouping of power, RF, clock, debug, and GPIO pins would improve clarity.
Footprint cross-check
Correct
  • Footprint contains pads 1–48 around the perimeter and exposed pad 49 at center.
  • Pin numbering proceeds consistently around the package and agrees with the symbol mapping.
  • Lead pitch is 0.5 mm.
  • Perimeter copper pads are approximately 0.254 × 0.813 mm, close to the datasheet recommended nominal land dimensions of about 0.30 × 0.75 mm.
  • Exposed pad is approximately 5.69 × 5.69 mm, consistent with the package exposed-pad range and close to the recommended 5.6 mm land.
  • Pin-1 marking is present.
Footprint concern
  • The center pad 49 itself includes F.Paste, while sixteen additional segmented paste polygons are also present. This likely produces a nearly full-size paste opening instead of only the intended segmented paste pattern. It is not a pin-map error, but it should be reviewed against the assembler’s stencil rules to avoid excessive solder and package float.
Overall assessment
The package selection, pad count, perimeter pad numbering, and nearly all symbol pin names match the official datasheet. The part should not be treated as fully verified until pin 47 is renamed to VLXSMPS, ground electrical types are corrected, and pin descriptions are populated. The exposed-pad solder-paste definition also warrants manufacturing review.

  • Scope

  • Existing part information

  • Key verified specifications

  • Symbol and pin-map cross-check

  • Correct

  • Mismatches and omissions

  • Footprint cross-check

  • Correct

  • Footprint concern

  • Overall assessment