Check this schematic component against the datasheet for [MPN] and assign the correct pin orientation, section, and terminal order without changing, replacing, renumbering, or remapping any pins. Remove the Pin Group property from all pins if it exists. Place Power pins first and Ground pins last. Within each section, distribute the pins as evenly as possible between the left and right sides; for example, split 10 pins as 5/5 and 11 pins as 5/6 or 6/5. If a section contains only one pin, leave it on the most appropriate side. Keep the symbol compact, balanced, and visually symmetrical. If a pin function is unclear, assign Unclear / Check datasheet, then apply all changes directly to the schematic component.
I’ll apply this to the current MPN, STM32C031K6T6. I’ll preserve every pin number and mapping, remove Pin Group, assign datasheet-based sections/types/orientations/orders, and rebalance the symbol with power first and ground last.
Updated the official datasheet URL and reorganized all 32 symbol pins without changing names, numbers, or mappings. Pins are balanced 16/16 left/right, Power is first, Ground last, and all Pin Group properties were removed.
The Part Datasheet Audit contains the full findings. Critical issue: the LQFP32 footprint appears scaled approximately 1000× too small; incorrect Logic/AND classification and missing package metadata were also flagged. An internal part-quality report was filed.
You’re correct—the footprint values are stored in meters, so 0.0008 m = 0.80 mm; there is no 1000× scaling error. I corrected the Part Datasheet Audit and withdrew the fabrication-blocking warning.
STM32C031K6T6 temperature code 6: -40 °C to +85 °C ambient, +105 °C maximum junction
12-bit ADC, up to 19 external + 2 internal channels for the K6 device
1 x I2C Fast-mode Plus, 1 x SPI / I2S, 2 x USART
Advanced-control timer, four general-purpose 16-bit timers, two watchdogs, SysTick
SWD debug
Package: 32-pin LQFP, 7 x 7 mm body, 0.80 mm pitch, 9 x 9 mm lead span
Metadata audit
Table
Field
Current state
Datasheet cross-check
Status
MPN
STM32C031K6T6
Exact match
Pass
Manufacturer
STMicroelectronics
Exact match
Pass
Pin count
32
K = 32 pins
Pass
Datasheet URL
Official ST PDF set
Correct
Pass
Description
STM32C031K6T6 only
Should describe the Cortex-M0+ MCU and principal memory/peripherals
Incomplete
Part Type
Integrated Circuits
Broadly valid
Pass
IC subtype
Logic
Device is a microcontroller, not a logic gate
Mismatch
Logic Function
AND
Not applicable to this MCU
Mismatch
Package property
Not explicitly set
Should state LQFP32, 7 x 7 mm, 0.80 mm pitch
Missing
Symbol style
Parametric v1
Appropriate for terminal organization
Pass
Symbol and pin audit
All 32 physical pin numbers remain present exactly once and match the LQFP32 column of datasheet Table 12. No pins were renamed, renumbered, replaced, or remapped.
The symbol terminals were reorganized into Power, Clock, Reset, GPIO Port A, GPIO Port B, GPIO Port C, and Ground sections. Terminal orders are unique from 1 through 32, with Power first and Ground last. Multi-pin sections are evenly split between left and right; the complete symbol is balanced 16 left / 16 right. Pin Group was removed from every terminal as requested.
Pin types and descriptions are now populated from the datasheet. Power is Power In, ground is Ground, and multiplexed GPIO pins are Bi-Directional. No unresolved pin functions remain.
Naming observations
The following existing terminal names are non-canonical concatenations but their physical numbers and functions match the datasheet:
PC14-OSCX_INPC14 -> datasheet name PC14-OSCX_IN (PC14), pin 2
PC15-OSCX_OUTPC15 -> datasheet name PC15-OSCX_OUT (PC15), pin 3
PA11PA9 -> datasheet name PA11 [PA9], pin 22
PA12PA10 -> datasheet name PA12 [PA10], pin 23
They were intentionally not renamed because the requested constraint prohibited changing pin names or mappings. Their Pin Description fields now explain the oscillator/remap functions.
Footprint audit
The footprint topology is consistent with an LQFP32: 32 perimeter pads, eight per side, and the pad sequence corresponds to the symbol pin numbers. The footprint asset and 3D model are labeled LQFP32_7X7_STM.
The geometry is correct when the stored layout dimensions are interpreted in meters and converted to the millimeter dimensions used by the datasheet. For example, a stored pitch of 0.0008 m equals the specified 0.80 mm. The earlier 1000x scale warning was a unit-conversion error and is withdrawn.
The datasheet footprint example specifies 0.80 mm pitch, 0.50 mm pad width, 1.20 mm pad length, 6.10 mm inner span, 9.70 mm outer span, and a 7.30 mm courtyard/body-related dimension. No footprint scaling mismatch is present.
Final mismatch list
Metadata
IC subtype is incorrectly classified as Logic.
Logic Function is incorrectly set to AND.
Description is too generic and omits the MCU function/specification summary.
Explicit package/case metadata is missing.
Non-critical naming
Four terminal names use concatenated formatting rather than the datasheet notation; pin numbers and mappings are correct, and descriptions now disambiguate them.
Recommended corrections
Change the IC subtype/classification from Logic to Microcontroller and remove the AND logic function metadata.
Add package metadata: LQFP32, 7 x 7 mm body, 0.80 mm pitch.
Expand the description to identify the 48 MHz Cortex-M0+ MCU, 32 KB Flash, 12 KB SRAM, ADC, timers, and communication interfaces.
Optionally normalize the four concatenated terminal names in a separate change only if pin-name changes are approved.