Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.
I’ll audit the part metadata, locate and attach the official ST datasheet if needed, then cross-check symbol pins, footprint geometry, and descriptions against it.
Audit of STL40DN3LLH5 metadata, official datasheet association, schematic symbol terminals, footprint pads, and pin descriptions.
Metadata reviewKey datasheet specifications
The official ST datasheet reviewed was DS7090 Rev 8 (July 2026). Values below were extracted from that PDF; the PDF text was OCR-derived in the review tool, so critical production use should retain the official PDF as the source of truth.
Dual N-channel automotive-grade power MOSFET
Drain-source voltage: 30 V
Continuous drain current: 40 A at TC = 25 °C; PCB/ambient-rated current: 11 A at TA = 25 °C and 7 A at TA = 100 °C
RDS(on): 16 mΩ typical / 18 mΩ maximum at VGS = 10 V, ID = 5.5 A
RDS(on): 20 mΩ typical / 25 mΩ maximum at VGS = 4.5 V, ID = 5.5 A
Audit complete. The official ST datasheet URL was already correctly set, so no metadata update was required. The part fails validation: the datasheet defines 8 physical pins, while the symbol/footprint expose 14 terminals with swapped source/gate assignments and incorrect drain numbering; a possible footprint unit-scale issue was also flagged.
Full findings and key specifications: Part Audit Report. I also filed an internal part-quality report for engineering review.
Already present and points to the official ST datasheet; no update needed
Lifecycle
Active
Confirmed on the official ST product page
Library terminal count
14
Mismatch with the datasheet's 8 physical pins
Key datasheet specifications
The official ST datasheet reviewed was DS7090 Rev 8 (July 2026). Values below were extracted from that PDF; the PDF text was OCR-derived in the review tool, so critical production use should retain the official PDF as the source of truth.
Dual N-channel automotive-grade power MOSFET
Drain-source voltage: 30 V
Continuous drain current: 40 A at TC = 25 °C; PCB/ambient-rated current: 11 A at TA = 25 °C and 7 A at TA = 100 °C
RDS(on): 16 mΩ typical / 18 mΩ maximum at VGS = 10 V, ID = 5.5 A
RDS(on): 20 mΩ typical / 25 mΩ maximum at VGS = 4.5 V, ID = 5.5 A
Gate threshold: 1.0 V minimum, 1.5 V typical at ID = 250 µA
Total gate charge: 4.5 nC typical at VDD = 15 V, ID = 11 A, VGS = 0 to 4.5 V
Thermal resistance: 3.0 °C/W junction-to-case; 32 °C/W junction-to-ambient on the specified 1 in², 2 oz copper FR-4 test board
Marking: 40DN3LH5
Packing: tape and reel, 3000-piece base/bulk quantity
Datasheet pinout
Table
Physical pin
Required function
1
S1
2
G1
3
S2
4
G2
5
D2
6
D2
7
D1
8
D1
Symbol and terminal mismatches
The current symbol exposes 14 independently numbered terminals rather than the 8 physical pins in the datasheet.
Current pin 1 is named S2; it must be S1.
Current pin 2 is named G2; it must be G1.
Current pin 3 is named S1; it must be S2.
Current pin 4 is named G1; it must be G2.
Current pins 5 and 6 are named as D1 pads; the datasheet assigns both to D2.
Current pin 7 is named as D2; the datasheet assigns it to D1.
Current pin 8 is named as D2; the datasheet assigns it to D1.
Current terminals numbered 9 through 14 do not exist as physical package pins in the datasheet.
All symbol terminals currently have unspecified electrical type and no descriptive pin-function text.
The symbol is therefore electrically unsafe to use as-is: it can swap the two MOSFET source/gate connections and assign drain copper to the wrong transistor.
Footprint review
The footprint contains 14 separate pad nodes named S1, S2, G1, G2, D1_1 through D1_5, and D2_1 through D2_5. Multiple copper shapes may legitimately be used to form the two exposed drain islands, but they must share the correct physical pin numbers/net identities rather than becoming unique package terminals 9–14.
The pad arrangement is broadly recognizable as a dual-island PowerFLAT 5x6 pattern, but the scene-tree reports coordinates and sizes such as 0.0025 mm and 0.0021 mm while claiming millimeter units. If interpreted literally, this is approximately 1000× too small. This may be a unit-reporting/import issue rather than the source footprint geometry; the underlying KiCad footprint must be checked against ST Figure 18 before release.
Package outline data reviewed from the datasheet includes a nominal 6.0 mm by 5.2 mm body family with 1.27 mm lead pitch and the PowerFLAT 5x6 double-island WF type R recommended footprint.
Disposition
Fail — do not publish or use this part as-is. Metadata and official datasheet association are good, but the symbol terminal mapping and footprint pad numbering do not match the manufacturer's pinout. A Flux part-quality report has been filed for engineering review.
Required corrections
Rebuild the terminal model around physical pins 1–8.
If the exposed islands use multiple pad primitives, assign those primitives to the appropriate shared physical pin numbers/net identities; do not expose pins 9–14.
Add clear pin descriptions and appropriate MOSFET pin electrical types.
Verify all footprint dimensions and pad locations directly against ST Figure 18, including the suspected unit-scale issue.
Re-render and independently verify the symbol and footprint before publishing.