MOSFET Part Audit

flux

Scoped audit: Completed Mutation performed
The current project now reports this URL. The published-library search index still shows the older empty Datasheet URL, so the published version/index has not yet synchronized with the project edit.
Part-level audit

Table

FieldCurrent value / status
NameSQJ128ELP-T1_GE3
MPNSQJ128ELP-T1_GE3 — correct
ManufacturerVishay Siliconix
Part typeTransistor
DescriptionDetailed automotive 30 V N-channel MOSFET description is present
Designator prefixU — questionable; MOSFET convention is normally Q
Package propertyNo explicit Package/Case property found
Datasheet URLUpdated to official Vishay PDF
LifecycleActive in Flux library
Terminal/pad count5
Distributor dataMouser and Verical listed; lowest indexed price $0.6193
Distributor part-number propertiesNone observed
BOMEmpty, expected for a standalone part project
AssetsCustom SVG symbol, KiCad footprint, and PPAK_SO8L_Option3.step 3D model
Metadata discrepancy
The direct project state contains manufacturer, part type, rich description, and the new Datasheet URL. The published library index still returns:
  • blank Manufacturer Name
  • blank Part Type
  • blank Datasheet URL
  • generic description SQJ128ELP-T1_GE3
This appears to be unpublished/stale indexed metadata rather than a failed project mutation.
Official datasheet evidence
Official document: Vishay Siliconix SQJ128ELP, document 77128, Rev. A, 28-Sep-2020. The -T1_GE3 ordering suffix corresponds to this base device.

Table

SpecificationOfficial value and conditions
ChannelN-channel, single MOSFET
VDS30 V
VGS±20 V
Continuous ID437 A at TC = 25 °C; 252 A at TC = 125 °C
Pulsed IDM595 A; pulse-test limitation applies
Continuous source current340 A
RDS(on), 10 V drive0.95 mΩ typical, 1.15 mΩ max, VGS = 10 V, ID = 15 A
RDS(on), 4.5 V drive1.38 mΩ typical, 1.66 mΩ max, VGS = 4.5 V, ID = 15 A
VGS(th)1.2 V min, 1.7 V typ, 2.2 V max at VDS = VGS, ID = 250 µA
Power dissipation500 W at TC = 25 °C; 166 W at TC = 125 °C
TJ / Tstg−55 °C to +175 °C
RθJC0.4 °C/W, junction-to-case/drain
RθJA42 °C/W on a 1-inch-square FR-4 PCB
PackagePowerPAK SO-8L, case outline 3
QualificationAEC-Q101; 100% Rg and UIS tested
The very high current and power ratings are case-temperature-limited ratings and are not directly achievable on an arbitrary PCB without adequate thermal design.
Symbol and terminal audit
Current terminals:

Table

PinCurrent nameCurrent typeOther terminal metadata
1SUnspecifiedNo description, group, section, orientation property, or order
2SUnspecifiedSame omissions
3SUnspecifiedSame omissions
4GUnspecifiedSame omissions
5DUnspecifiedSame omissions
All five pins have explicit custom symbol-position vectors. Direction is inferred from position: pins 1 and 4 render on the left; pins 2, 3, and 5 on the right. No suffixes or independent sub-symbols exist.
Critical pinout mismatch
The official package pinout is:
  • Pin 1: Gate
  • Pins 2, 3, 4: Source
  • Pin 5 / large exposed drain pad: Drain
Current project mapping is:
  • Pin 1: Source
  • Pins 2, 3: Source
  • Pin 4: Gate
  • Pin 5: Drain
Therefore, pins 1 and 4 are swapped in both the terminal metadata and footprint-to-terminal mapping. This is a critical functional error. It was reported but not corrected because the task explicitly prohibited symbol/footprint changes.
Symbol-quality findings
  • The custom SVG appears malformed or inappropriate as an electrical MOSFET symbol: it renders as a large rectangular graphic with block-like shapes rather than a recognizable N-channel MOSFET.
  • Electrical types are all Unspecified.
  • Pin descriptions are absent.
  • Pin Group, Section, Pin Orientation, and Terminal Order properties are absent.
  • The symbol positions are populated, but the logical pin assignment is wrong for pins 1 and 4.
Footprint audit
Footprint asset: SQJ128ELP-T1_GE3.kicad_mod
Embedded value: PowerPAK_SO-8L_3_VIS
Current copper pads

Table

PadCurrent functionCenterSize
1S−1.905, +3.6068 mm0.5334 × 1.524 mm
2S−0.635, +3.6068 mm0.5334 × 1.524 mm
3S+0.635, +3.6068 mm0.5334 × 1.524 mm
4G+1.905, +3.6068 mm0.5334 × 1.524 mm
5D0, −1.1303 mm4.1148 × 4.9022 mm
  • Lead pitch is correctly 1.27 mm.
  • There are four small lead pads and one large exposed drain pad.
  • Pad 5’s drain/tab mapping is conceptually correct.
  • Pad 1/4 logical mappings are incorrect as described above.
  • Copper pads include F.Cu, F.Paste, and F.Mask.
  • Silkscreen, fabrication outline, courtyard, pin-1 marks, footprint asset, and a STEP model are present.
Mechanical comparison
Official PowerPAK SO-8L case-outline limits include:
  • Body D1: 4.80–5.00 mm
  • Body E1: 4.27–4.47 mm
  • Overall E: 6.05–6.25 mm
  • Height A: 1.00–1.10 mm
  • Pitch: 1.27 mm BSC
  • Exposed drain dimensions include b2: 4.00–4.20 mm and D2: 3.86–4.06 mm
The footprint fabrication body is approximately 5.0038 × 4.4704 mm, essentially at the upper case-outline limits. The large pad’s 4.1148 mm dimension lies within the 4.00–4.20 mm exposed-drain dimension range.
However, the current pad geometry is not an exact match to Vishay’s current recommended-land-pattern dimensions:
  • Current small pads: 0.5334 × 1.524 mm
  • Vishay recommended pattern shows approximately 0.68 mm lead-pad width and 1.10 mm lead-pad length.
  • The current pattern appears to be an older/generic Accelerated Designs land pattern rather than a direct implementation of Vishay document 78020.
The datasheet extraction did not preserve every dimension arrow unambiguously, so the exact orientation of all recommended thermal-pad dimensions remains uncertain. Nevertheless, the lead-pad dimensional difference is clear enough to flag for manual CAD-overlay review.
Geometry/tool inconsistency
The raw KiCad footprint payload contains normal millimetre values, but structured computed layout nodes report values scaled by 0.001, and the footprint image renders empty. This suggests a unit-conversion/rendering defect in the imported footprint representation or layout inspection path. The raw footprint payload is the more credible geometry source, but actual board instantiation should be verified before using this part.
Mismatches and uncertainties
  1. Critical: Pin 1 and pin 4 are swapped; official is 1=G, 4=S.
  2. Critical: Footprint terminal mapping repeats the same pin 1/4 swap.
  3. Major: Custom schematic symbol is not a recognizable MOSFET symbol.
  4. Major: All terminal electrical types are Unspecified.
  5. Major: Terminal descriptions, groups, sections, explicit orientations, and ordering are absent.
  6. Major: Imported footprint geometry shows a probable 1000× unit/rendering inconsistency in structured layout output.
  7. Moderate: Lead-pad dimensions differ from Vishay’s current recommended land pattern.
  8. Moderate: No explicit Package/Case property is populated, despite the footprint and description identifying PowerPAK SO-8L.
  9. Moderate: Designator prefix is U; Q would normally be appropriate.
  10. Metadata: Published-library metadata remains stale/blank relative to the current project.
  11. Uncertainty: The 3D model filename indicates PowerPAK SO-8L option 3, but its dimensional alignment could not be established from the available structured output.
No mismatches were corrected beyond the requested Datasheet URL update.

flux

Audit complete. I added the official Vishay datasheet URL: https://www.vishay.com/docs/77128/sqj128elp.pdf.
Key findings
  • 30 V N-channel automotive MOSFET, PowerPAK SO-8L
  • ±20 V VGS; RDS(on) max 1.15 mΩ at 10 V and 1.66 mΩ at 4.5 V
  • AEC-Q101 qualified; −55 °C to +175 °C
  • Critical mismatch: pins 1 and 4 are swapped. Datasheet: 1=Gate, 2/3/4=Source, 5=Drain; current part: 1=Source, 4=Gate
  • Symbol is not a conventional MOSFET symbol; pin types and descriptions are missing
  • Footprint lead pads differ from Vishay’s current recommended land pattern and require CAD-overlay review
  • Package property is missing, and the U designator prefix should normally be Q
No pin or geometry changes were made. I filed a part-quality report for the critical mapping and asset issues.
Fix pinout and metadata
Fix critical mismatches
Update terminal metadata
Check land pattern
Run final review
S
Pin Number
1
G
Pin Number
4
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SQJ128ELP-T1_GE3

SQJ128ELP-T1_GE3 thumbnail
Automotive N-Channel Power MOSFET – 30 V N-channel TrenchFET® Gen IV power MOSFET optimized for automotive power distribution, battery management systems (BMS), motor drives, DC-DC converters, load switching, and high-current embedded power applications. Features a 30 V drain-to-source voltage (VDS), 437 A continuous drain current (TC = 25°C), and ultra-low RDS(on) of 1.16 mΩ maximum at VGS = 10 V (1.66 mΩ maximum at VGS = 4.5 V) for exceptionally low conduction losses. Offers ±20 V gate-to-source voltage, 595 A pulsed drain current, 500 W maximum power dissipation, low gate charge, optimized Qgd/Qgs ratio for fast switching, and an integrated body diode for high-efficiency switching applications. Qualified to AEC-Q101, 100% Rg and UIS tested, and specified for operation over a −55°C to +175°C junction temperature range. Housed in a PowerPAK® SO-8L surface-mount package.
#Vishay #SQJ128ELPT1GE3 #SQJ128ELP #NChannelMOSFET #TrenchFET #PowerMOSFET #DCDCConverter #BatteryManagement #MotorDrive #AutomotiveElectronics #PowerPAKSO8L #EmbeddedSystems

Properties

SQJ128ELP-T1_GE3

Vishay Siliconix

Transistor

vishay.com/docs/77128/sqj128elp.pdf

U

parametric-v1

Pricing & Availability

DPN

Stock

Qty 1

2

0–15

$0.6298–$0.7001

3

0

$0.00

1

0

$1.0083

1

22K

$2.52

1

15

$0.6193

Controls