Part Audit Review

A

adrian95

Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.

flux

I’ll audit the part metadata, locate and attach the official datasheet if needed, then verify the symbol, footprint, and pin descriptions against it and report any mismatches.
Created a project doc

SPD5118-Y1B000NCG8 Part Information Audit

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Reviewed project metadata, published library metadata, the nine-terminal schematic symbol, the default footprint asset, and the attached SPD...

flux

Audit complete. Pin numbering and the 9-contact DFN footprint arrangement are substantially correct, but the package is incorrectly labeled Module, the AND logic classification and 0°C to +70°C range are wrong, and all pins lack electrical types and datasheet-derived descriptions; the existing datasheet URL was already populated, so I left it unchanged.
Full findings: SPD5118-Y1B000NCG8 Part Information Audit
Fix metadata and pins
Update footprint notes
Run ERC DRC
Rename ground pins
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SPD5118-Y1B000NCG8 Part Information Audit
Audit scope
Reviewed project metadata, published library metadata, the nine-terminal schematic symbol, the default footprint asset, and the attached SPD5108/SPD5118 datasheet. The attached datasheet URL was already populated, so it was not changed. An official Renesas product page and part-detail page were also found; the downloadable full datasheet appears access-controlled by Renesas.
Current part information

Table

FieldCurrent valueAssessment
Manufacturer part numberSPD5118-Y1B000NCG8Correct
ManufacturerRenesasCorrect
Pin/contact count9 terminalsCorrect when counting 8 perimeter leads plus exposed thermal pad pin 9
Package propertyModuleIncorrect / too generic
Datasheet package8-DFN / 9-contact thermally enhanced PSON-8, NCG8P1, MO-229 variant, 2.0 x 3.0 x 0.75 mm, 0.5 mm pitchShould replace “Module”
Part typeIntegrated Circuits / LogicBroad category acceptable, but subtype is misleading
Logic functionANDIncorrect; this is not an AND gate
Datasheet URLIHS-hosted Renesas SPD5108/SPD5118 PDFPresent and readable; no update required by the request
DescriptionDDR5 SPD hub EEPROM with integrated temperature sensorFunctionally correct overall, but temperature range is wrong in the library description
Datasheet key specifications
  • DDR5 SPD Hub with host/local bus isolation.
  • 1024-byte nonvolatile EEPROM organized as 16 independently write-protectable blocks of 64 bytes.
  • Host and local interfaces support I2C up to 1 MHz and I3C Basic up to 12.5 MHz.
  • VDDSPD operating range: 1.7 to 2.0 V, 1.8 V nominal.
  • VIO operating range: 0.95 to 1.05 V, 1.0 V nominal; pin 7 requires at least 1.0 uF to ground even when externally powered.
  • Case operating temperature: -40 to +125 C; NVM write operation: -40 to +95 C.
  • Integrated temperature sensor: 0.25 C resolution; typical accuracy varies by range (typically ±0.5 C at 75 to 95 C, ±1 C at 40 to 125 C, and ±2 C across -40 to 125 C).
  • Package: 8-DFN with exposed pad, 2.0 x 3.0 x 0.75 mm, 0.5 mm pitch, nominal exposed pad 1.5 x 1.5 mm.
Pin cross-check

Table

PinSymbol nameDatasheet name/functionResult
1LSDALSDA/RFU, local-bus I2C/I3C Basic data, I/OMapping correct; description/type metadata missing
2HSDAHost-bus I2C/I3C Basic data, I/OMapping correct; description/type metadata missing
3HSCLHost-bus I2C/I3C Basic input clock, inputMapping correct; description/type metadata missing
4LSCLLSCL/RFU, local-bus output clock, outputMapping correct; description/type metadata missing
5VDDSPD1.8 V input power supplyMapping correct; description/type metadata missing
6GND_1VSS, groundElectrical mapping correct; symbol name should preferably be VSS rather than generic GND_1
7VIO1.0 V LDO output/external input; minimum 1.0 uF requiredMapping correct; critical capacitor requirement absent from pin description
8HSAHost-bus address inputMapping correct; description/type metadata missing
9GND_2Exposed thermal pad, ground plane connectionElectrical mapping correct; should preferably be named EP/VSS or Thermal Pad rather than GND_2
All nine terminal objects currently have Pin Type: Unspecified and do not contain datasheet-derived Pin Description properties. This weakens symbol clarity and ERC behavior even though the pin numbers and functional names are substantially correct.
Footprint cross-check
  • Footprint identifier/description: SON50P300X200X80-9N-D, described as 8-DFN, 2.0 x 3.0 x 0.75 mm, 0.5 mm pitch, exposed pad 1.5 x 1.5 mm.
  • Perimeter pad numbering and arrangement are consistent with the datasheet bottom-view assignment: pins 1-4 on one side, pins 5-8 on the opposite side, and pin 9 centered.
  • Perimeter land size: 0.30 x 0.85 mm; row-to-row pad centers: 2.90 mm; pitch: 0.50 mm.
  • Exposed land is implemented as 1.60 x 1.60 mm, while the package exposed metal is specified as 1.50 x 1.50 mm. This may be a deliberate solder-land allowance, but the accessible datasheet extraction did not provide a recommended PCB land-pattern table, so exact compliance cannot be confirmed.
  • Fab outline is 3.0 x 2.0 mm, matching the package body with the footprint rotated relative to the datasheet’s dimension naming.
  • Pin-1 marking is present.
Definite mismatches
  1. Package or Case Code = Module is wrong; use 8-DFN (NCG8P1), 2.0 x 3.0 x 0.75 mm, 0.5 mm pitch or the closest canonical package string.
  2. Library subtype/logic metadata indicating Logic Function = AND is wrong.
  3. The library description states a 0 C to +70 C commercial range, but the exact Y1B000NCG8 ordering variant is rated for -40 C to +125 C operation.
  4. Every schematic terminal has Pin Type = Unspecified; assign Power, Ground, Input, Output, or Bidirectional according to the datasheet.
  5. Datasheet-derived pin descriptions are absent.
Naming/clarity issues
  • Rename pin 6 from GND_1 to VSS.
  • Rename pin 9 from GND_2 to EP/VSS or Thermal Pad (GND).
  • Consider retaining /RFU in pins 1 and 4 descriptions to match family documentation while keeping the SPD5118 functional names LSDA and LSCL visible.
Items needing authoritative land-pattern confirmation
  • Confirm whether the 1.60 x 1.60 mm exposed PCB land and 0.30 x 0.85 mm perimeter lands match Renesas package drawing PSC-4244-01 or an IPC-derived recommended land pattern. The package body and pitch are otherwise consistent.
Datasheet/source notes
  • Existing attached PDF: https://4donline.ihs.com/images/VipMasterIC/IC/RNCC/RNCC-S-A0013011026/RNCC-S-A0013481722-1.pdf?hkey=52A5661711E402568146F3353EA87419
  • Official product page: https://www.renesas.com/en/products/spd5118
  • Official exact-part page found through Renesas search results: SPD5118-Y1B000NCG8 part details.

  • Audit scope

  • Current part information

  • Datasheet key specifications

  • Pin cross-check

  • Footprint cross-check

  • Mismatches and recommended corrections

  • Definite mismatches

  • Naming/clarity issues

  • Items needing authoritative land-pattern confirmation

  • Datasheet/source notes