Part Audit Review

Thought for 10 sec

Yes. I’ll group every pin once by its primary function—Power, Ground, Inputs, and Outputs—without duplicates, and keep each pin’s Section matched to its Pin Group while completing the datasheet audit.

Worked for 4 mins 18 sec

flux

The metadata and pin grouping are updated. I’m doing a final read-back of all 14 terminals and checking the official TI package/pin data before closing the audit.

Worked for 2 mins 28 sec

Created a project doc

Part Audit Report

View Document

Manufacturer: Texas Instruments MPN: SN74LV6T14QPWRQ1

flux

Completed the full audit and grouped every pin exactly once: Inputs, Outputs, Power, and Ground. Pin mapping and the TSSOP-14 footprint match TI documentation; the incorrect wettable-flank claim was removed.

The existing datasheet field already contained a valid mirrored PDF, so it was not replaced; the canonical TI URL is recorded.
The terminal metadata is correct, but the generated symbol still has a visual rendering/asset issue that should be checked before publishing.

Full findings: Part Audit Report

Fix symbol and review

Fix symbol rendering

Update datasheet URL

Rerun ERC DRC

Check BOM sourcing

Files

Pins

Symbol

Layout

Preview

Part Audit Report

Official identification

Manufacturer: Texas Instruments
MPN: SN74LV6T14QPWRQ1
Function: Automotive-qualified six-channel Schmitt-trigger inverter with enhanced-input level translation capability
Package: PW / PW0014A, 14-pin TSSOP, 0.65 mm lead pitch
Official datasheet: https://www.ti.com/lit/ds/symlink/sn74lv6t14-q1.pdf
Product page: https://www.ti.com/product/SN74LV6T14-Q1

Key specifications

Recommended supply voltage: 1.6 V to 5.5 V
Input voltage range: 0 V to 5.5 V
Output voltage range: 0 V to VCC
Operating free-air temperature: -40 C to +125 C
Output current under recommended conditions: +/-3 mA at 1.6-2.0 V, +/-7 mA at 2.25-2.75 V, and +/-15 mA at 3.3-5.0 V
Up to 150 Mbps operation is advertised at 3.3 V or 5 V VCC
AEC-Q100 Grade 1 family qualification

Pin verification and grouping

Table

Pin	Name	Type	Primary group	Description
1	1A	Input	Inputs	Channel 1 Schmitt-trigger input A
2	1Y	Output	Outputs	Channel 1 inverted output Y
3	2A	Input	Inputs	Channel 2 Schmitt-trigger input A
4	2Y	Output	Outputs	Channel 2 inverted output Y
5	3A	Input	Inputs	Channel 3 Schmitt-trigger input A
6	3Y	Output	Outputs	Channel 3 inverted output Y
7	GND	Ground	Ground	Ground reference
8	4Y	Output	Outputs	Channel 4 inverted output Y
9	4A	Input	Inputs	Channel 4 Schmitt-trigger input A
10	5Y	Output	Outputs	Channel 5 inverted output Y
11	5A	Input	Inputs	Channel 5 Schmitt-trigger input A
12	6Y	Output	Outputs	Channel 6 inverted output Y
13	6A	Input	Inputs	Channel 6 Schmitt-trigger input A
14	VCC	Power In	Power	Positive supply voltage

Every physical pin is assigned to exactly one primary group. Section matches Pin Group for all terminals. Inputs are oriented Left with orders 1-6; Outputs are oriented Right with orders 1-6; VCC is Power/Top/order 1; GND is Ground/Bottom/order 10.

Footprint cross-check

14 surface-mount pads: correct
Pad pitch: 0.65 mm, correct
Current pad size: 0.45 mm x 1.475 mm, effectively consistent with TI's approximately 0.45 mm x 1.5 mm land recommendation
Current row span: approximately 5.876 mm, consistent with the TI recommended land-pattern span near 5.8 mm
PW0014A package body: 5.0 mm x 4.4 mm nominal, 1.2 mm maximum height
Pin-1 silk indicator is present

Corrections and mismatches

Corrected the description/package metadata to standard PW TSSOP-14.
Removed the implication that the PWRQ1 ordering code itself uses wettable flanks. TI offers wettable flanks on the separate BQA/WQFN package; PW is the TSSOP option.
Added Pin Description, Pin Type, Pin Group, Section, Pin Orientation, and Terminal Order to all terminals.
The stored Datasheet URL was already populated with a mirrored copy, so the conditional request to add a URL was not triggered. The canonical TI URL is recorded above; an attempted replacement did not persist through the available metadata interface.
Terminal metadata reads back correctly, but the generated symbol has shown a renderer/asset presentation issue. This does not indicate a pin-number or footprint-mapping mismatch, but visual symbol rendering should be rechecked before publishing.
A generic project DRC error was reported without accessible item-level detail; it was not identified as a footprint geometry error.

Official identification
Key specifications
Pin verification and grouping
Footprint cross-check
Corrections and mismatches