Part Datasheet Audit

flux

Part audited
Project metadata identifies the part as:
  • Manufacturer: Texas Instruments
  • MPN: SN74AHCT1G125DBVR
  • Package / case: SOT-23-5
  • Part type: Integrated Circuit
  • Designator prefix: IC
  • Footprint asset: SOT95P280X145-5N.kicad_mod
  • 3D model asset: SN74AHCT1G125DBVR.stp
  • Symbol asset: SN74AHCT1G125DBVR Symbol.svg
  • Datasheet URL: TI datasheet PDF in project properties
The TI package referenced in the datasheet is DBV0005A, SOT-23-5, 1.45 mm max height.
1. Symbol / terminal audit
The project symbol contains 5 terminals, matching the TI DBV0005A / SN74AHCT1G125 pin count.
Symbol terminals found in project

Table

Project terminalPin numberSymbol positionProject pin typeTI functionTI electrical type
~OE1x = -71.5, y = 14.5UnspecifiedOutput EnableInput
A2x = -71.5, y = 0.5UnspecifiedInput AInput
GND3x = -71.5, y = -14.5UnspecifiedGround pinPower / supply
Y4x = 71.5, y = 14.5UnspecifiedOutput YOutput
VCC5x = 71.5, y = 0.5UnspecifiedPower pinPower / supply
Symbol grouping / orientation
From the symbol pin positions:
  • Left side:
    • Pin 1: ~OE
    • Pin 2: A
    • Pin 3: GND
  • Right side:
    • Pin 4: Y
    • Pin 5: VCC
This is a logical-symbol arrangement, not a physical package arrangement. It places inputs and ground on the left, output and VCC on the right.
No explicit symbol sections, gates, groups, or pin-orientation properties were found beyond the coordinate positions.
Symbol mismatches / issues
  1. All project pin types are Unspecified.
    TI defines:
    • Pin 1 OE: Input
    • Pin 2 A: Input
    • Pin 3 GND: Ground / supply
    • Pin 4 Y: Output
    • Pin 5 VCC: Power / supply
  2. ~OE naming differs slightly from TI table.
    TI names the pin OE, with the function “Output Enable.” The project uses ~OE, which implies active-low enable. That is likely semantically helpful, but it is not an exact textual match to the datasheet pin-name table.
  3. Terminal designator prefix mismatch.
    The project-level part metadata says designator prefix is IC, but each terminal object has Designator Prefix: P. This may be normal internal terminal metadata, but it is a metadata mismatch if interpreted literally.
2. Footprint audit Footprint asset
The PCB footprint used by the project is:
  • SOT95P280X145-5N.kicad_mod
This footprint name indicates:
  • SOT package style
  • 95P = 0.95 mm nominal pin pitch
  • 280 = likely 2.80 mm nominal package span / width class
  • 145 = 1.45 mm max height class
  • 5N = 5 terminals
This is consistent with TI’s DBV0005A SOT-23-5, 1.45 mm max height package family.
Pads found in project
The project PCB index contains five footprint pads:

Table

Pad designator in projectCorresponding pin
~OE1
A2
GND3
Y4
VCC5
The pad-to-pin mapping therefore matches the project symbol pin numbers and TI pinout:

Table

TI pinTI nameProject symbolProject pad
1OE~OE~OE
2AAA
3GNDGNDGND
4YYY
5VCCVCCVCC
Pad count
  • Project footprint pad count: 5
  • TI DBV0005A terminal count: 5
This matches.
Pad coordinates / dimensions / layers
The indexed PCB data confirms the existence of the pad nodes, but it does not expose the individual pad coordinates, pad dimensions, pad shapes, or layer assignments in the search result.
Therefore, from the available project index I can confirm:
  • Pads exist for all five terminals.
  • Pad names map correctly to symbol/TI pins.
  • The footprint asset is named for a 0.95 mm pitch, 5-pin SOT package.
But I cannot verify exact project pad coordinates or pad sizes from the indexed data.
Expected TI DBV0005A dimensions from datasheet
From the fetched TI datasheet for DBV0005A SOT-23-5:
Package outline
  • Package: DBV0005A
  • Type: SOT-23, 5-pin
  • Max height: 1.45 mm
  • Nominal package size including leads: 2.9 mm × 2.8 mm
  • Nominal body size: 2.9 mm × 1.6 mm
  • Pitch:
    • 0.95 mm
    • TI drawing shows 2× 0.95 mm, total span across three pins of 1.9 mm
  • Lead width:
    • 0.3 mm to 0.5 mm
  • Lead length / terminal dimension shown:
    • 0.3 mm to 0.6 mm
  • Body width:
    • 1.45 mm to 1.75 mm
  • Body length:
    • 2.75 mm to 3.05 mm
TI example board layout
TI’s example land pattern gives:
  • 5× pads
  • Pad size: 1.1 mm × 0.6 mm
  • Pitch: 0.95 mm
  • Overall land-pattern dimension shown: 2.6 mm
  • Longitudinal pin span shown: 1.9 mm
  • Typical pad corner radius: R0.05
  • Solder mask guidance:
    • Non-solder-mask-defined preferred
    • 0.07 mm max / min mask clearance guidance shown
Pitch / row spacing comparison

Table

ItemProject footprintTI DBV0005A
Pin count5 pads found5 pins
PitchFootprint name indicates 95P = 0.95 mm0.95 mm
Package height classFootprint name includes 1451.45 mm max
Package width/span classFootprint name includes 280TI package size includes 2.8 mm width including pins
Pad sizeNot exposed in indexTI example: 1.1 mm × 0.6 mm
Row spacing / land-pattern overall widthNot exposed in indexTI example shows 2.6 mm overall land-pattern dimension
LayersNot exposed in indexTI land pattern assumes top copper / mask / paste for SMT
The footprint asset name is strongly consistent with TI DBV0005A, but the indexed project data does not provide enough detail to verify exact pad sizes and coordinates.
3. Outlines, courtyard, and pin-1 marking
The indexed PCB data confirms only the presence of the footprint asset:
  • SOT95P280X145-5N.kicad_mod
It does not expose the footprint’s:
  • Fabrication outline
  • Silkscreen outline
  • Courtyard outline
  • Assembly outline
  • Pin-1 dot, bevel, marker, or index-area graphic
  • Text reference/value placement
TI DBV0005A pin-1 marking
The TI package drawing shows:
  • Pin numbering:
    • Pins 1–3 on one side
    • Pins 4–5 on the opposite side
  • A clear Pin 1 index area on the package outline drawing.
Because the project index does not expose the footprint drawing primitives, I cannot confirm whether the KiCad footprint includes a silkscreen pin-1 marker or if it matches the TI index-area convention.
4. Overall comparison against TI DBV0005A SOT-23-5 Matches
The project data matches TI DBV0005A in the important high-level ways:
  • Correct manufacturer part number: SN74AHCT1G125DBVR
  • Correct package family: SOT-23-5
  • Correct pin count: 5
  • Correct symbol-to-pad pin mapping:
    • 1 ~OE
    • 2 A
    • 3 GND
    • 4 Y
    • 5 VCC
  • Correct functional order vs TI pin table.
  • Footprint asset name SOT95P280X145-5N is consistent with:
    • 0.95 mm pitch
    • 2.8 mm package span
    • 1.45 mm max package height
    • 5 terminals
Mismatches / concerns
  1. Pin electrical types are missing.
    All symbol terminals are Unspecified, while TI defines inputs, output, ground, and power.
  2. Exact footprint geometry could not be verified from indexed PCB data.
    The project index lists pad nodes but not pad coordinate, dimension, shape, or layer details.
  3. Pin-1 marker and outline could not be verified.
    The index does not expose silkscreen/fab/courtyard primitives.
  4. Name difference: ~OE vs TI OE.
    Likely intentional to show active-low behavior, but not an exact datasheet name match.
  5. Metadata prefix inconsistency.
    Project-level designator prefix is IC; individual terminal objects show designator prefix P.
Conclusion
The project’s symbol and footprint are broadly consistent with TI SN74AHCT1G125DBVR in DBV0005A SOT-23-5. The pin count and pad-to-pin mapping match the TI datasheet exactly. The footprint asset name also matches the expected 0.95 mm pitch, 2.8 mm SOT-23-5, 1.45 mm height package class.
The main audit issues are metadata/detail issues rather than obvious pinout errors:
  • Symbol pin electrical types are all Unspecified.
  • Exact pad geometry, layers, outlines, courtyard, and pin-1 marker are not exposed in the searchable project data, so they cannot be fully verified.
  • ~OE differs from TI’s OE naming but is functionally understandable.
  • Terminal-level prefix P differs from project-level IC prefix.Audit complete. MPN/package/pin count and mapping are correct: SN74AHCT1G125DBVR, TI DBV SOT-23-5, pins 1–5 = active-low OE, A, GND, Y, VCC; key specs are 4.5–5.5 V operation, TTL thresholds (VIH 2 V, VIL 0.8 V), ±8 mA rated output drive, up to 9.5 ns propagation delay at 50 pF, and −40°C to 125°C.
Flags: all symbol electrical pin types are Unspecified; exact footprint pad dimensions and pin-1 marker could not be conclusively verified, although its 0.95 mm-pitch SOT-23-5 identity and mapping match TI DBV0005A; the description contains corrupted text (4.5 ??? 5.5 V). A Datasheet URL was already present, so I left it unchanged; the canonical TI URL is https://www.ti.com/lit/ds/symlink/sn74ahct1g125.pdf.
Fix issues and verify
Fix metadata issues
Verify footprint geometry
Use canonical datasheet
Run part review
GND
Pin Number
3
A
Pin Number
2
~OE
Pin Number
1
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SN74AHCT1G125DBVR

SN74AHCT1G125DBVR thumbnail
Single Non-Inverting 3-State Buffer IC – Single non-inverting CMOS buffer with a 3-state output and TTL-compatible inputs for signal buffering, bus interfacing, memory address/data buses, digital logic control, and embedded systems. Operates from a 4.5 V to 5.5 V supply and features 8 mA source/sink output drive capability, active-low output enable (OE), and high-impedance output mode for shared bus applications. Provides high-speed operation with a typical propagation delay of 8.5 ns, low power CMOS operation, latch-up performance exceeding 250 mA, and ESD protection compliant with HBM and CDM standards. Specified for operation over a −40°C to +125°C temperature range and housed in a compact 5-pin SOT-23 (DBV) surface-mount package.
#TexasInstruments #SN74AHCT1G125DBVR #SN74AHCT1G125 #LogicBuffer #TriStateBuffer #BusBuffer #TTLCompatible #CMOSLogic #SignalBuffer #DigitalLogic #SOT23 #EmbeddedSystems

Properties

SN74AHCT1G125DBVR

Texas Instruments

Integrated Circuit

ti.com/lit/ds/symlink/sn74ahct1g125.pdf

IC

SOT-23-5

parametric-v1

Pricing & Availability

DPN

Stock

Qty 1

3

0–1.6K

$0.0443–$0.0755

1

8K

$0.1056

1

0

$0.14

1

4K

$0.00

2

1.6K

$0.0509–$0.0759

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