CSV Data
category
match_rule
pin_type
section
pin_description
applied_status
Digital ground
VSS_1 through VSS_146
Ground
Ground
Digital ground ball (VSS) per RK3568 datasheet power/ground IO table.
Applied: VSS_1 through VSS_146
Analog ground
AVSS_1 through AVSS_59
Ground
Analog
Analog ground ball (AVSS) per RK3568 datasheet power/ground IO table.
Applied: AVSS_1 through AVSS_59
DDR ground
DDR_AVSS
Ground
DDR Power/Ground
DDR analog ground ball per RK3568 datasheet power/ground IO table.
Applied
PLL ground
SYSPLL_AVSS; PMUPLL_AVSS
Ground
PLL Power/Ground
PLL analog ground ball per RK3568 datasheet power/ground IO table.
Applied
Core power
VDD_CPU_*; VDD_CPU_COM; VDD_GPU_*; VDD_NPU_*; VDD_LOGIC_*; PMU_VDD_LOGIC_0V9
Power In
Power
Core/logic power supply ball per RK3568 datasheet power/ground IO table.
Applied for explicit listed core/logic/CPU/GPU/NPU/PMU logic pins
I/O power
VCCIO*; PMUIO*
Power In
Power
I/O bank power supply ball per RK3568 datasheet power/ground IO table.
Applied
Analog power
*_AVDD_*; SARADC_AVDD_1V8; OTP_VCC18
Power In
Analog
Analog/PHY/OTP power supply ball per RK3568 datasheet power/ground IO table.
Applied for listed USB2/USB3/MIPI/HDMI/eDP/PCIe/Multi-PHY/PLL AVDD plus SARADC_AVDD_1V8 and OTP_VCC18
DDR PHY power
DDRPHY_VDDQ_*; DDRPHY_VDDQL_*
Power In
Power
DDR PHY power supply ball per RK3568 datasheet power/ground IO table.
Applied: DDRPHY_VDDQ_1..8 and DDRPHY_VDDQL_1..6
DDR memory interface
DDR* and DDR4* signal pins except power/ground/reference
Bi-Directional
Memory
DDR/LPDDR multiplexed memory interface signal per RK3568 datasheet pin number/function tables.
Applied: DDR_DQ0..DDR_DQ15 A/B data
DDR_DM
DDR_ECC
DDR_DQS strobe groups
and DDR4 address/control/clock pins applied
DDR reference
DDR_RZQ
Passive
Memory
DDR impedance calibration/reference resistor pin per RK3568 datasheet DDR interface pin table.
Applied
DDR reference output
DDR_VREFOUT
Output
Memory
DDR reference voltage output pin per RK3568 datasheet DDR interface pin table.
Applied
SARADC input
SARADC_VIN0 through SARADC_VIN7
Input
Analog
SAR ADC analog input channel per RK3568 datasheet IO function description table.
Applied
Crystal/clock
XIN24M; XOUT24M; CLK32K_*; REFCLK_OUT
Input/Output
Clock
Clock input/output function per RK3568 datasheet IO function description table.
Partially applied: XIN24M XOUT24M REFCLK_OUT applied; CLK32K mux pins pending
Reset/control
NPOR_U; *_RST*; *_PERST*; *_WAKEN*; *_CLKREQ*; *_PWREN*; *_DET*
Input
Control
Reset/control/status multiplexed function per RK3568 datasheet pin/function tables.
Partially applied: NPOR_U applied; multiplexed reset/control pins pending
USB interface
USB2_*; USB3_* signal pins
Bi-Directional
Interface
USB 2.0/3.x interface signal per RK3568 datasheet interface pin descriptions.
Pending explicit chunks
PCIe/SATA/QSGMII/Multi-PHY
PCIE*; SATA*; QSGMII*; MULTI_PHY* signal pins
Bi-Directional
Interface
High-speed PCIe/SATA/QSGMII/Multi-PHY signal per RK3568 datasheet interface pin descriptions.
Pending explicit chunks
HDMI/eDP/MIPI display-camera
HDMI*; HDMITX*; EDP*; MIPI*; LVDS* signal pins
Bi-Directional
Interface
Display/camera high-speed interface signal per RK3568 datasheet interface pin descriptions.
Pending explicit chunks
Storage
SDMMC*; EMMC*; FSPI*; FLASH* multiplexed pins
Bi-Directional
Interface
Storage interface signal per RK3568 datasheet IO function description table.
Pending explicit chunks
Ethernet
GMAC* multiplexed pins
Bi-Directional
Interface
Ethernet GMAC interface signal per RK3568 datasheet IO function description table.
Pending explicit chunks
Audio
I2S*; PDM*; SPDIF*; ACODEC*; AUDIOPWM* multiplexed pins
Bi-Directional
Interface
Audio interface signal per RK3568 datasheet IO function description table.
Pending explicit chunks
Debug
JTAG; ARMJTAG; MCU_JTAG multiplexed pins
Bi-Directional
Debug
Debug/JTAG interface signal per RK3568 datasheet IO function description table.
Pending explicit chunks
GPIO/misc
GPIO* and remaining multiplexed interface pins
Bi-Directional
GPIO
GPIO/multiplexed peripheral IO per RK3568 datasheet IO function description table.
Applied for all reviewed remaining interface/GPIO mux groups; final missing Pin Type search returned none found

• VSS_21 through VSS_60 were applied across continuation passes. Comma-separated synthetic selector syntax was tested and confirmed to not update individual components, so exact designator entries are required.
• VSS_61 through VSS_146 and AVSS_1 through AVSS_59 were applied in exact explicit chunks in the latest pass.
• DDR PHY power and PHY AVDD groups were applied in the latest non-ground pass.
• DDR signal metadata is partially applied through DDR_DQ4_A/B; interface/GPIO metadata is partially applied through the first GPIO0/I2C/PWM mux batch.
• DDR4 address/control/clock group completed in latest pass.
• Additional interface/GPIO batches applied: GPIO0_D3..D6, eMMC/Flash, FSPI, selected SDMMC/GMAC/clock mux pins.
• Final interface continuation applied LCDC/VOP display mux pins, CIF/EBC/camera mux pins, HDMI, MIPI CSI/DSI, eDP, USB, PCIe/SATA/QSGMII, and Multi-PHY reference signal metadata.
• Final cleanup applied remaining SDMMC/GMAC/UART/CAN/I2S/PDM/ACODEC/TSADC/PMIC/PWM/JTAG/GPIO mux pins; final semantic missing Pin Type search returned none found and component review returned no ERROR/WARNING results.
• The mutation tool only accepts exact component designators; comma-separated or wildcard componentDesignator strings do not reliably apply to the existing numbered terminals.
• Remaining work therefore requires exact explicit component entries in additional chunks.