Part Verification and Datasheet Update

Worked for 2 mins 27 sec

Completed the part review and created the detailed findings in Part Verification Report.

Summary: the datasheet URL was already set, the symbol pin names/numbers match the PIC16F84A-20I/P datasheet, but pin types/descriptions are missing and the footprint is still placeholder geometry rather than a valid 18-pin 300 mil PDIP footprint.

adrian95

Fix the pin types, add pin descriptions, set PDIP package metadata, and build the correct footprint.

Thought for 5 sec

flux

I’ll update the terminal metadata from the datasheet, set the PDIP package property cleanly, then replace the placeholder pads with a proper 18-pin 300 mil PDIP footprint and verify it.

Worked for 35 sec

flux

I found the package property is already set to 18-PDIP; now I’m applying datasheet-backed pin metadata and parametric DIP footprint rules.

Worked for 2 mins 34 sec

flux

Pin metadata is corrected and the footprint rules are applied; I’m doing a final schematic/layout readback now.

Thought for 2 mins 12 sec

flux

Done.

Updated all 18 terminal pin types to Flux-standard values and added datasheet-backed pin descriptions.
Verified project package metadata is set to Package or Case Code = 18-PDIP.
Built the correct 18-pin 300 mil DIP footprint with 2.54 mm pitch, 7.62 mm row spacing, through-hole pads, and rectangular pin-1 marker.
Verified the schematic metadata and layout footprint rules by readback.

Open item: the generated footprint asset uses 0.76 mm drills / 1.16 mm pads internally, while the explicit pad rules are set to 0.8 mm drills; if you want a different house-standard DIP pad stack, I can tune that next.

Tune pads and review

Tune DIP pads

Run ERC/DRC

Update review report

Check footprint dimensions

Files

Pins

Symbol

Layout

3D View

Part Verification Report: PIC16F84A-20I/P

Reviewed project metadata

Project/part name: PIC16F84A-20I_P
Manufacturer Part Number: PIC16F84A-20I/P
Manufacturer: Microchip
Description: 8-Bit Microcontroller
Part Type: Integrated Circuits
Pin/pad count: 18 schematic terminals and 18 PCB pads
Datasheet URL property: already set to a Microchip PIC16F84A PDF hosted in project storage: 818973619155f3f3b4c9a5228269c5643ae0b9d9af3cc5ebbf5b4b21911374c5.pdf

Because a datasheet URL was already present, I did not overwrite it. The content identifies itself as Microchip Technology PIC16F84A Data Sheet DS35007B.

Key datasheet specs

Device: PIC16F84A, 18-pin Enhanced FLASH/EEPROM 8-bit microcontroller
Ordering code decoded: PIC16F84A-20I/P = 20 MHz, industrial temperature, PDIP package, normal VDD limits
CPU: 35 single-word instructions; most instructions single-cycle except branches
Speed: DC to 20 MHz clock input; 200 ns instruction cycle
Program memory: 1024 words
RAM: 68 bytes
Data EEPROM: 64 bytes
I/O: 13 user-configurable I/O pins
Timers/interrupts: TMR0, RB0/INT external interrupt, PORTB interrupt-on-change, data EEPROM write complete interrupt
ICSP: via RB6 serial programming clock and RB7 serial programming data
Supply: datasheet feature list says 2.0 V to 5.5 V for commercial/industrial; DC characteristics excerpt for PIC16F84A-20 shows 4.0 V or 4.5 V minimum depending oscillator configuration, 5.5 V maximum
Temperature: I suffix = -40 °C to +85 °C
Package: P suffix = 18-lead PDIP, 300 mil, JEDEC MS-001 equivalent
PDIP pitch: 2.54 mm; nominal body length 22.80 mm; shoulder-to-shoulder width nominal 7.94 mm; row spacing range 7.87 mm to 10.92 mm

Pinout cross-check

Table

Pin	Datasheet name/function	Symbol terminal present	Schematic pin type
1	RA2, I/O, TTL	RA2	Unspecified
2	RA3, I/O, TTL	RA3	Unspecified
3	RA4/T0CKI, I/O, Schmitt trigger; Timer0 clock input; output is open-drain	RA4/T0CKI	Unspecified
4	MCLR, input/programming voltage; active-low reset	~MCLR	Unspecified
5	VSS, ground reference	VSS	Unspecified
6	RB0/INT, I/O; external interrupt	RB0/INT	Unspecified
7	RB1, I/O, TTL	RB1	Unspecified
8	RB2, I/O, TTL	RB2	Unspecified
9	RB3, I/O, TTL	RB3	Unspecified
10	RB4, I/O; interrupt-on-change	RB4	Unspecified
11	RB5, I/O; interrupt-on-change	RB5	Unspecified
12	RB6, I/O; interrupt-on-change; ICSP clock	RB6	Unspecified
13	RB7, I/O; interrupt-on-change; ICSP data	RB7	Unspecified
14	VDD, positive supply	VDD	Unspecified
15	OSC2/CLKOUT, oscillator output/CLKOUT	OSC2/CLKOUT	Unspecified
16	OSC1/CLKIN, oscillator or external clock input	OSC1/CLKIN	Unspecified
17	RA0, I/O, TTL	RA0	Unspecified
18	RA1, I/O, TTL	RA1	Unspecified

Footprint cross-check

Expected from datasheet/order code: 18-lead 300 mil PDIP, through-hole footprint, 2.54 mm pitch, two rows.

Observed layout: 18 pad nodes exist, but every pad currently has default placeholder geometry: position (0,0), size 0.0016 mm x 0.0016 mm, circular pad shape, top layer with annular layers top/bottom. No explicit footprint ruleset is defined.

Mismatches / issues flagged

Package metadata is incomplete: project properties do not include an explicit Package or Case Code value, though the MPN suffix /P indicates 18-lead PDIP.
All terminal Pin Type properties are Unspecified. Power pins should be Power/Ground, OSC1 should be Input, OSC2 should be Output, MCLR should be Input/Power or Input, and GPIO pins should be Bidirectional/I/O where supported by Flux pin typing.
Pin descriptions are not populated on the terminals. The terminal names and pin numbers match the datasheet, but detailed datasheet descriptions are missing.
Footprint geometry is not a valid PDIP-18 footprint. Pads are all located at the origin with near-zero size and no 2.54 mm pitch/two-row geometry.
MCLR is named ~MCLR while the datasheet labels it MCLR and describes it as active-low reset. This is an acceptable schematic convention, not a mismatch.

Verdict

The schematic symbol pin numbers and visible terminal names match the Microchip PIC16F84A PDIP/SOIC pinout for pins 1-18. The main problems are missing pin metadata/descriptions and an invalid placeholder footprint that does not represent the required 18-lead 300 mil PDIP package.

Reviewed project metadata
Key datasheet specs
Pinout cross-check
Footprint cross-check
Mismatches / issues flagged
Verdict