PCF2131 Part Review


/silicon-yard/pcf2131tfy
Official NXP PCF2131 datasheet says the HLSON16 exposed pad must be left floating, but the Flux part models schematic terminal 17 and the footprint center pad as VSS. This can cause incorrect grounding.
check and correct if necessary according to the datasheet
I’ll verify the exposed-pad requirement against the official NXP datasheet, inspect terminal 17 and the center footprint pad, then correct the part and re-check it.
I’m validating the exact package note and inspecting both logical and physical pad mappings before changing anything.
The datasheet confirms the exposed pad must be left electrically floating. I’m now identifying its exact terminal and footprint-node mappings so the fix is limited to pad 17.
Inspecting the current pin name, electrical mapping, and center-pad binding before applying the correction.
Pad 17 was already renamed EP in both symbol and footprint; I’ve now explicitly classified it as Not Connected and added the instruction to leave it floating. I’m performing the final read-back check.
Verified and corrected. NXP specifies the HLSON16 exposed pad must remain floating.
  • Terminal/pad 17 is named EP, not VSS.
  • Set pin type to Not Connected.
  • Added description: “Exposed pad; leave floating.”
  • Filed a part-quality report for the original incorrect VSS modeling.

INTB
Pin Number
12
BBS
Pin Number
14
SDI
Pin Number
3
CLKOUT
Pin Number
6
TS1
Pin Number
8
SDO
Pin Number
4
IFS
Pin Number
1
EP
Pin Number
17
VSS
Pin Number
7
SCL
Pin Number
2
TS4
Pin Number
11
SDA/CE
Pin Number
5
VDD
Pin Number
15
INTA
Pin Number
13
TS2
Pin Number
9
VBAT
Pin Number
16
TS3
Pin Number
10
PCF2131TFY Part Review
Date: 2026-07-14
Scope
Reviewed available Flux part information for PCF2131TFY: MPN, package, pin count, description, project/component properties, schematic terminals, footprint pads, and pin descriptions. Cross-checked against the official NXP datasheet and package information.
Sources
Metadata Review

Table


FieldFlux part value observedDatasheet / official sourceStatus
Manufacturer Part NumberPCF2131TFYPCF2131TFY is the orderable part number for product type PCF2131TFMatch
ManufacturerWas empty; updated to NXP SemiconductorsNXP SemiconductorsUpdated / match
Datasheet URLWas empty; updated to official NXP PDFhttps://www.nxp.com/docs/en/data-sheet/PCF2131.pdfUpdated / match
DescriptionPCF2131TFYNano-power highly accurate RTC with integrated quartz crystalIncomplete
Package propertyNo clear package property observedHLSON16, SOT1992-1, 16 terminals, 0.5 mm pitch, 4.5 mm x 3.5 mm x 1.45 mm bodyMissing / incomplete
Pin / terminal count17 terminals / pads16 electrical terminals plus exposed pad; exposed pad should be left floatingMismatch / misleading
Library classificationSearch result showed Integrated Circuits / Logic and logic function ANDRTC/calendar IC with I2C/SPI, battery backup, timestamp inputsMismatch
Key Datasheet Specs

Table


SpecValue
DevicePCF2131 CMOS RTC/calendar with integrated TCXO and 32.768 kHz quartz crystal
Orderable partPCF2131TFY
PackageHLSON16, SOT1992-1
Body4.5 mm x 3.5 mm x 1.45 mm
Pitch0.5 mm
Operating temperature-40 °C to +85 °C
VDD operating range1.2 V to 5.5 V
VBAT operating range1.2 V to 5.5 V
Absolute max VDD/VBAT-0.5 V to +6.5 V
Typical supply current64 nA at VDD = 3.3 V in low-power inactive configuration
AccuracyTypical ±3 ppm from -40 °C to +85 °C with temperature compensation
I2C400 kHz Fast-mode, 7-bit target address 0b1010011 / 0x53
SPI4-line SPI, max 6.5 MHz for VDD = 3.3 V to 5.5 V; max 0.5 MHz for VDD = 1.2 V to 3.3 V
CLKOUTPush-pull programmable square wave, 32.768 kHz default down to 1 Hz; high-Z when disabled
InterruptsINTA and INTB open-drain, active LOW
Timestamp inputsTS1-TS4 active LOW with internal 500 kΩ pull-up
Backup functionVBAT backup supply, BBS battery-backed output voltage; VBAT must be tied to VSS if battery switch-over is not used
Exposed padLeave floating
Pinout Cross-Check
Pins 1 through 16 match the official NXP pin table.

Table


PinFlux terminalDatasheet symbolDatasheet descriptionStatus
1IFSIFSInterface selector input; VSS selects SPI, VDD selects I2CMatch
2SCLSCLCombined serial clock input for I2C-bus and SPI-busMatch
3SDISDISPI serial data input; connect to VSS if I2C is selectedMatch
4SDOSDOSPI serial data output, push-pull; leave open or connect to VSS if I2C is selectedMatch
5SDA/CESDA/CEI2C serial data I/O and SPI chip-enable input, active LOWMatch
6CLKOUTCLKOUTClock output, push-pullMatch
7VSSVSSGround supply voltageMatch
8TS1TS1Timestamp input, active LOW, internal 500 kΩ pull-upMatch
9TS2TS2Timestamp input, active LOW, internal 500 kΩ pull-upMatch
10TS3TS3Timestamp input, active LOW, internal 500 kΩ pull-upMatch
11TS4TS4Timestamp input, active LOW, internal 500 kΩ pull-upMatch
12INTBINTBInterrupt B output, open-drain, active LOWMatch
13INTAINTAInterrupt A output, open-drain, active LOWMatch
14BBSBBSOutput voltage, battery-backedMatch
15VDDVDDSupply voltageMatch
16VBATVBATBattery supply voltage backup; connect to VSS if switch-over not usedMatch
17VSSExposed PadExposed pad; leave floatingMismatch
Symbol / Pin Description Findings
  • All terminal Pin Type properties are currently Unspecified.
  • Terminal-specific Pin Description properties were not present.
  • Recommended library-quality improvements:
    • IFS: Input / configuration.
    • SCL: Input clock.
    • SDI: Input.
    • SDO: Output, push-pull.
    • SDA/CE: Bidirectional / input depending selected interface mode.
    • CLKOUT: Output, push-pull.
    • VSS: Ground.
    • TS1-TS4: Input / timestamp input.
    • INTA/INTB: Output, open-drain, active LOW.
    • BBS: Power output / battery-backed output.
    • VDD: Power input.
    • VBAT: Backup power input.
    • Exposed pad: mechanical / no-connect / floating, not VSS.
Footprint Review
Existing footprint asset: PCF2131TFY.kicad_mod, value text SON_131TFY_NXP.
Observed footprint geometry from the KiCad asset payload:

Table


FeatureExisting footprintNXP SOT1992-1 package / footprint infoStatus
Peripheral pads16 pads16 terminalsMatch
Pitch~0.500 mm0.5 mmMatch
Peripheral pad size0.8128 mm x 0.254 mmNXP solderable pad guideline 0.9 mm x 0.27 mm; solder-mask opening 1.0 mm x 0.37 mmSlightly smaller than NXP guideline
Peripheral pad x-location±1.651 mmNXP guideline includes side callout around 2 x 1.7 mmClose
Center pad2.0574 mm x 3.8608 mmNXP solderable area 2.0 mm x 3.8 mm; mask opening 2.1 mm x 3.9 mmClose
Center pad name/netVSS / pad 17Exposed pad: leave floatingMismatch
Package bodyFab outline about 3.505 mm x 4.496 mm3.5 mm x 4.5 mm nominal bodyMatch
The footprint is broadly consistent with the HLSON16 / SOT1992-1 package geometry, but the peripheral pad dimensions are smaller than the official NXP solderable-pad recommendation. The most important footprint issue is the center exposed pad being modeled as VSS instead of floating/no-connect.
Mismatches / Issues Flagged
  1. High severity: exposed pad modeled as VSS.
    • Datasheet: exposed pad must be left floating.
    • Current part: schematic terminal 17 is named VSS; footprint center pad 17 is also named VSS.
    • Risk: downstream boards may unintentionally connect the exposed pad to ground, contrary to NXP guidance.
  2. Pin count is misleading.
    • Datasheet package is HLSON16: 16 electrical terminals plus an exposed pad.
    • Flux part has 17 terminals. This is only acceptable if terminal 17 is clearly modeled as an exposed/no-connect mechanical pad, not as VSS.
  3. Pin descriptions and electrical types are incomplete.
    • Every terminal is currently Pin Type: Unspecified.
    • Datasheet-backed pin descriptions should be added for usability and ERC quality.
  4. Description is incomplete.
    • Current description is just the MPN.
    • Recommended description: NXP PCF2131TFY nano-power highly accurate RTC/calendar with integrated 32.768 kHz quartz crystal, I2C/SPI interface, battery backup, HLSON16/SOT1992-1 package.
  5. Package metadata is incomplete.
    • Add package/case detail: HLSON16 / SOT1992-1, SMD, 0.5 mm pitch, 4.5 mm x 3.5 mm x 1.45 mm body.
  6. Library classification appears wrong.
    • Search metadata classified the part as Logic / AND.
    • It should be classified as an RTC / clock/timing integrated circuit.
  7. Peripheral footprint pads are slightly smaller than NXP recommendation.
    • Existing: 0.8128 mm x 0.254 mm.
    • NXP solderable guideline: 0.9 mm x 0.27 mm.
    • This is a moderate footprint-compliance issue; the center pad size is close to NXP guidance.
  1. Rename or remodel pad/terminal 17 as EP / EXPOSED_PAD / NC, and ensure it is not net-tied to VSS.
  2. Add datasheet-backed Pin Description and Pin Type properties for all terminals.
  3. Update the part description and package metadata to mention RTC/calendar, I2C/SPI, battery backup, HLSON16/SOT1992-1.
  4. Correct the library taxonomy/classification from Logic/AND to RTC / clock/timing IC if the platform exposes that field for editing.
  5. Consider adjusting peripheral footprint pads to NXP’s 0.9 mm x 0.27 mm solderable-pad guideline if strict manufacturer land-pattern compliance is desired.
  • Scope

  • Sources

  • Metadata Review

  • Key Datasheet Specs

  • Pinout Cross-Check

  • Symbol / Pin Description Findings

  • Footprint Review

  • Mismatches / Issues Flagged

  • Recommended Next Actions