Part Datasheet Audit
Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.
Thought for 5 sec
I’ll audit the part metadata, locate the official onsemi datasheet if needed, update the Datasheet property, then verify the symbol pins and SO-8 footprint against it.
Worked for 3 mins 3 sec
Created a project doc
Part Datasheet Audit
Part Datasheet Audit
Scope and sources
Reviewed the NTMD6P02R2G part metadata, all eight schematic terminals, the imported SOIC-8 footprint, and the attached 3D model reference. Cross-check source: official onsemi datasheet, publication order NTMD6P02R2/D, Rev. 6 (January 2026): https://www.onsemi.com/pdf/datasheet/ntmd6p02r2-d.pdf
The existing Datasheet URL property is already populated with the official onsemi PDF (
Available part information
Datasheet pinout cross-check
https://www.onsemi.com/pub/Collateral/NTMD6P02R2-D.PDF), so no property update was required. The newer canonical onsemi URL above resolves to the same datasheet family.The symbol-to-pad numbering is correct. However, every terminal currently has Pin Type = Unspecified and no explicit functio...
Audit complete. The existing Datasheet property already links to the official onsemi PDF, so no update was needed; pin numbering and SOIC-8 footprint mapping are correct.
Flagged issues: incorrect Diodes classification, incomplete description, unspecified pin types/descriptions, and nonstandard
IC prefix. Full specs and comparisons are in Part Datasheet Audit.Fix metadata and pins
Change designator prefix
Compare footprint options
Verify 3D alignment
Part Datasheet Audit
Scope and sources
Reviewed the NTMD6P02R2G part metadata, all eight schematic terminals, the imported SOIC-8 footprint, and the attached 3D model reference. Cross-check source: official onsemi datasheet, publication order NTMD6P02R2/D, Rev. 6 (January 2026): https://www.onsemi.com/pdf/datasheet/ntmd6p02r2-d.pdf
The existing Datasheet URL property is already populated with the official onsemi PDF (
https://www.onsemi.com/pub/Collateral/NTMD6P02R2-D.PDF), so no property update was required. The newer canonical onsemi URL above resolves to the same datasheet family.Available part information
Table
| Field | Current value | Audit |
|---|---|---|
| MPN | NTMD6P02R2G | Correct orderable Pb-free suffix variant of NTMD6P02R2 |
| Manufacturer | ON Semiconductor | Correct; current branding is onsemi |
| Package | 8-SO / surface mount | Correct at a high level; datasheet calls it SOIC-8 NB, CASE 751-07, STYLE 11 |
| Pin count | 8 | Correct |
| Compliance | Pb-Free | Correct for the G suffix |
| Lifecycle | Active | Consistent with library metadata |
| Designator prefix | IC | Usable but nonstandard; Q is preferable for a dual MOSFET |
| Part type | Diodes / Other | Incorrect classification; this is a dual P-channel power MOSFET array |
| Description | Feature list only | Features are relevant, but the description should identify the device as a dual P-channel, −20 V power MOSFET in SOIC-8 |
| Datasheet URL | Official onsemi PDF present | Correct; no update needed |
Datasheet pinout cross-check
Table
| Pin | Datasheet function | Current terminal label | Result |
|---|---|---|---|
| 1 | Source 1 | S1 | Match |
| 2 | Gate 1 | G1 | Match |
| 3 | Source 2 | S2 | Match |
| 4 | Gate 2 | G2 | Match |
| 5 | Drain 2 | D2_1 | Electrically correct; suffix is an internal duplicate-pad label |
| 6 | Drain 2 | D2_2 | Electrically correct; suffix is an internal duplicate-pad label |
| 7 | Drain 1 | D1_1 | Electrically correct; suffix is an internal duplicate-pad label |
| 8 | Drain 1 | D1_2 | Electrically correct; suffix is an internal duplicate-pad label |
The symbol-to-pad numbering is correct. However, every terminal currently has Pin Type = Unspecified and no explicit functional description. Gate pins should be described as MOSFET control inputs, sources as Source 1/2, and drains as Drain 1/2. For clarity in downstream use, the duplicate drain terminal names could remain unique internally while their displayed descriptions identify the common drain connection.
Footprint cross-check
Current footprint asset:
SOIC127P600X175-8N.kicad_mod.- Pin pitch: 1.27 mm — matches datasheet.
- Body nominal dimensions represented: approximately 4.9 × 3.9 × 1.75 mm — consistent with datasheet limits of 4.80–5.00 × 3.80–4.00 × 1.35–1.75 mm.
- Lead span: footprint naming and geometry target approximately 6.0 mm, matching the datasheet 5.80–6.20 mm range.
- Pad numbering/orientation: standard counter-clockwise SOIC-8 numbering and matches STYLE 11 pin assignment.
- Current pads: 0.70 × 1.525 mm at 1.27 mm pitch. The onsemi example soldering footprint shows approximately 0.60 × 1.52 mm pads. The 0.10 mm width increase is a normal library/IPC land-pattern allowance, not an electrical pinout mismatch, but it is not an exact reproduction of the manufacturer example.
- Pin-1 marking exists in the footprint fabrication/silkscreen geometry.
- A STEP model is attached. This audit verified the model reference exists, but did not establish dimensional alignment from the rendered mesh alone.
Key electrical specifications
Table
| Parameter | Datasheet value |
|---|---|
| Device type | Dual P-channel power MOSFET |
| Drain-source voltage, VDSS | −20 V |
| Gate-source voltage, VGS | ±12 V continuous |
| RDS(on), VGS = −4.5 V, ID = −6.2 A | 27 mΩ typical, 33 mΩ maximum |
| Gate threshold, VGS(th) | −0.6 V min, −0.88 V typ, −1.20 V max at ID = −250 µA |
| Total gate charge | 20 nC typical, 35 nC maximum at VDS = −16 V, VGS = −4.5 V, ID = −6.2 A |
| Pulsed drain current | Up to −40 A under specified pulse conditions |
| Continuous drain current | Layout/thermal dependent: −4.8 A to −7.8 A at 25 °C under datasheet test-board conditions |
| Junction temperature | −55 °C to +150 °C |
| RθJA | 62.5, 98, or 166 °C/W depending on copper area and test condition |
| Package | SOIC-8 NB, CASE 751-07, STYLE 11 |
The headline “6 A” rating is condition-dependent. Board copper area and steady-state thermal limits must be used when selecting actual continuous current.
Flagged mismatches and recommended corrections
Material mismatches
- Part Type is wrong: currently
Diodes / Other; should be a MOSFET/transistor array category. - Description is incomplete: it lists marketing features but does not state the fundamental function, polarity, voltage, or package.
- Terminal metadata is incomplete: all pins are
Unspecifiedand lack functional descriptions.
Minor / convention issues
- Designator prefix
ICis nonstandard:Qis more conventional for MOSFETs, though changing it is not necessary for electrical correctness. - Drain labels use unique suffixes: electrically correct, but user-facing descriptions should make clear that pins 5–6 are common Drain 2 and pins 7–8 are common Drain 1.
- Pad width differs from the manufacturer example: 0.70 mm versus 0.60 mm; acceptable as an IPC-style land-pattern choice, but not an exact manufacturer-footprint copy.
Overall result
The critical electrical mapping is correct: eight pads, SOIC-8 geometry, and all source/gate/drain pin numbers agree with the official datasheet. The main deficiencies are semantic metadata and terminal descriptions rather than a dangerous pinout or footprint error.
Scope and sources
Available part information
Datasheet pinout cross-check
Footprint cross-check
Key electrical specifications
Flagged mismatches and recommended corrections
Material mismatches
Minor / convention issues
Overall result