NAU7802SGI Review
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Make the functional group more general.
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Add a Section property to all pins, and apply the same value used in the Pin Group property to each pin's Section property.
Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.
Thought for 20 sec
I’ll generalize the pin groups, mirror each Pin Group into Section, and set Terminal Order/Orientation with Power first/top and Ground last/bottom while distributing the other groups left/right.
Worked for 2 mins 22 sec
Updated the pin organization to more general groups: Power, Analog, Interface, and Ground.
Open items:
- None.
Suggested next steps:
- Review the symbol visually to confirm the left/right grouping looks natural.
- Publish/update the part if the grouping matches your convention.
Arrange and review
Arrange symbol
Run part review
Update review file
Publish readiness check
NAU7802SGI Part Review
Date: 2026-07-17
Sources
- Official Nuvoton datasheet used for review: https://www.nuvoton.com/export/resource-files/en-us--DS_NAU7802_DataSheet_EN_Rev2.6.pdf
- Nuvoton product page: https://www.nuvoton.com/products/smart-home-audio/audio-converters/precision-adc-series/nau7802sgi/
Part Metadata Reviewed
Table
| Field | Project value / review result |
|---|---|
| Manufacturer Part Number | NAU7802SGI |
| Manufacturer | Nuvoton Technology Corporation |
| Description | Precision low-power 24-bit sigma-delta ADC with PGA and 2-wire I2C-compatible interface for bridge sensors. |
| Package | SOP-16, 150 mil, 10 x 4 mm ordering dimension |
| Pin count | 16 |
| Datasheet property | Updated from missing/blank state using the official Nuvoton Rev. 2.6 datasheet URL. Flux stores a local datasheet asset for the part after update. |
| Part type | Integrated Circuit |
Key Datasheet Specs
Table
| Spec | Value |
|---|---|
| Function | Precision low-power 24-bit sigma-delta ADC for bridge/sensor measurement |
| Channels | Dual differential analog input channels |
| Resolution | 24-bit, no missing codes |
| ENOB | Up to 23-bit effective precision |
| PGA gain | Programmable x1, x2, x4, x8, x16, x32, x64, x128 |
| Supply voltage | DVDD 2.7 V to 5.5 V; AVDD 2.7 V to DVDD |
| AVDD/LDO | Programmable AVDD off or 2.4 V to 4.5 V; minimum 10 mA LDO output drive at 3.0 V |
| Standby / power-down current | <1 uA standby; typ. 0.2 uA, max. 1 uA power-down |
| Output data rates | 10, 20, 40, 80, 320 SPS |
| RMS noise | 50 nV at 10 SPS and PGA=128; 150 nV at 80 SPS and PGA=128 |
| Reference range | External differential reference 0.1 V to 5 V |
| Clock | Internal 4.9152 MHz RC oscillator or external 4.9152 MHz crystal |
| Interface | 2-wire I2C-compatible interface; SCLK up to 100 kHz standard mode / 400 kHz fast mode |
| I2C address | 7-bit address 0101010 |
| Operating temperature | -40 C to +85 C |
| Package | SOP-16 150 mil / PDIP-16 / QFN-16 family; NAU7802SGI is SOP-16 green package |
Pin Grouping Applied
Each physical pin is assigned to exactly one primary group. Section is set equal to Pin Group for every pin.
Table
| Pin | Name | Group | Pin Type | Datasheet function |
|---|---|---|---|---|
| 1 | REFP | Reference | Input | Positive reference input |
| 2 | VIN1N | Analog | Input | Channel 1 inverting analog input |
| 3 | VIN1P | Analog | Input | Channel 1 non-inverting analog input |
| 4 | VIN2N | Analog | Input | Channel 2 inverting analog input |
| 5 | VIN2P | Analog | Input | Channel 2 non-inverting analog input |
| 6 | VBG | Reference | Output | High-impedance reference voltage output and bypass |
| 7 | REFN | Reference | Input | Negative reference input |
| 8 | AVSS | Ground | Ground | Analog ground |
| 9 | DVSS | Ground | Ground | Digital ground |
| 10 | XIN | Clock | Input | External crystal oscillator input, typically 4.9152 MHz |
| 11 | XOUT | Clock | Output | External crystal oscillator output |
| 12 | DRDY | Digital Interface | Output | Data-ready output indicating conversion complete |
| 13 | SCLK | Digital Interface | Input | Serial data clock input for 2-wire interface; datasheet notes open-drain behavior |
| 14 | SDIO | Digital Interface | Bi-Directional | Serial data input/output for host communication, open-drain data line |
| 15 | DVDD | Power | Power In | Digital power supply, 2.7 V to 5.5 V |
| 16 | AVDD/LDO | Power | Power In | Analog supply / programmable LDO output; external AVDD 2.7 V to 5.5 V when LDO off |
Symbol Cross-Check
Result: pass.
- Symbol has 16 terminals, matching NAU7802SGI SOP-16.
- Pin numbers 1 through 16 match the datasheet pin table.
- Pin names match the datasheet: REFP, VIN1N, VIN1P, VIN2N, VIN2P, VBG, REFN, AVSS, DVSS, XIN, XOUT, DRDY, SCLK, SDIO, DVDD, AVDD/LDO.
- Pin descriptions and electrical types were updated from the datasheet.
- Functional grouping was updated using broad groups with no duplicate physical pin assignments.
Footprint Cross-Check
Result: nominal pass.
- Footprint asset: SOIC127P600X175-16N / 16L SOP 150 mil.
- Pad count: 16.
- Pad pitch in the footprint payload: 1.27 mm.
- Pad arrangement: two rows with pins 1-8 on one side and pins 9-16 on the opposite side, matching SOP-16 numbering convention.
- Footprint fab body outline is approximately 3.9 mm x 9.9 mm, consistent with the datasheet ordering dimension of 10 x 4 mm for NAU7802SGI.
- Row spacing and pad length are consistent with a 150 mil SOP/SOIC-style land pattern.
Mismatches / Risks Flagged
- No pin-number, pin-name, or symbol terminal-count mismatch was found.
- No obvious footprint pad-count or nominal package-family mismatch was found.
- The datasheet text extraction exposed the package family and ordering dimensions but not the full SOP-16 tolerance table in searchable text; the footprint was therefore checked against the visible datasheet ordering package and standard SOP-16 150 mil geometry present in the footprint payload.
- QFN-only exposed pad pin 17 is not applicable to NAU7802SGI SOP-16 and is correctly not present in this 16-pin part.
Follow-Up Recommendations
- If manufacturing tolerance-level validation is required, visually inspect the PDF package drawing or compare against Nuvoton's full mechanical drawing image for SOP-16 150 mil.
- For schematic usability, consider whether to split AVSS and DVSS into separate power/ground subgroups in future variants; they are currently both grouped under Ground as requested with no duplicates.
- Keep SCLK as Input and SDIO as Bi-Directional; both are part of the open-drain 2-wire interface and require suitable pullups in the application schematic.
Sources
Part Metadata Reviewed
Key Datasheet Specs
Pin Grouping Applied
Symbol Cross-Check
Footprint Cross-Check
Mismatches / Risks Flagged
Follow-Up Recommendations