Terminal Audit Complete

adrian95

adrian95

flux

Perform an exhaustive direct read of all 289 terminal components in the current part project, paging as needed. Audit and FIX any issue so: exactly 289 remain; every terminal has nonblank Pin Group, Section equal to Pin Group, valid Orientation; no Sub-symbol Designator Suffix was created; Terminal Order is integer, unique and exactly 1..N within each group; all VSS_* and DCDC_GND_* are Ground/Bottom; no power or ground terminal is in any GPIO group; all power groups and DCDC/PMU are Top; all other terminals match the broad groups already established. Preserve names, Pin Numbers, Symbol Pin Positions and all unrelated properties. After fixes, re-read all 289 and report group counts and validation results.

flux

I’ll page through all 289 terminals, audit every required field and grouping rule, apply only targeted property fixes, then re-read the full set and validate counts, ordering, orientations, and preservation constraints.

flux

The exhaustive audit found the project already compliant, so no writes were made. I’m now independently re-reading the terminal set to confirm the final inventory and constraints before closing.

flux

Exhaustive paged audit and final re-read completed for all 289 terminals. No fixes were required; every validation passed, including group/section equality, valid orientation, blank suffixes, consecutive unique per-group ordering, and power/ground rules. Protected properties remained unchanged.
Group counts: GPIO EMC B1 42; Ground 37; GPIO AD 36; GPIO EMC B2 21; DCDC/PMU 18; GPIO DISP B2 16; GPIO LPSR 16; GPIO DISP B1 12; GPIO SD B2 12; Power 3V3 12; GPIO SNVS 10; Core/1V0 Power 9; SNVS/LPSR Power 8; Clocks 6; GPIO SD B1 6; MIPI CSI 6; MIPI DSI 6; USB 6; Power 1V8 4; Reset Boot Control 4; Analog/Reference 2. Total: 289.
Review and document
Check symbol rendering
Export pin table
Audit datasheet mapping

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Part Audit Report
Scope and sources
Reviewed the MIMXRT1173CVM8A part metadata, all available symbol/terminal information, PCB footprint structure, and the attached 3D model. Primary source: NXP IMXRT1170IEC, Rev. 5 (01/2024), official industrial data sheet: https://www.nxp.com/docs/en/data-sheet/IMXRT1170IEC.pdf. Official product page: https://www.nxp.com/part/MIMXRT1173CVM8A.
Part identity and key specifications

Table

ItemVerified value
ManufacturerNXP
MPNMIMXRT1173CVM8A
Devicei.MX RT1173 crossover MCU / processor
CPUArm Cortex-M7 at 800 MHz + Cortex-M4 at 400 MHz
On-chip RAM2 MB without ECC or 1.75 MB with ECC
Package289-pin MAPBGA, NXP package code VM
Body / pitch14 × 14 mm, 0.8 mm pitch, 17 × 17 full ball matrix
Package height1.52 mm maximum; drawing identifies 14 × 14 × 1.37 mm nominal package
Ball diameter0.38–0.48 mm package solder-ball diameter (not the PCB land diameter)
TemperatureIndustrial, Tj −40 °C to +105 °C
Major interfaces2× USB 2.0 OTG, 3× CAN-FD, 1× GbE AVB, 1× 10/100 Ethernet IEEE 1588, 2× SD/eMMC, 12× UART, 6× I2C, 6× SPI, MIPI CSI/DSI, parallel LCD/CSI
Analog2× 12-bit ADC blocks, 1× 12-bit DAC, 4× ACMP
SecurityHAB, CAAM, IEE, OTFAD, SNVS, PUF and tamper support
Metadata review
Correct
  • Manufacturer and MPN match the official NXP ordering code.
  • Part type and description broadly match an i.MX RT1170-family 32-bit dual-core crossover MCU.
  • Pin count is 289.
  • An official NXP datasheet URL is already populated, so no Datasheet property update was required.
  • Footprint filename BGA289C80P17X17_1400X1400X152.kicad_mod encodes the correct nominal package family, 0.8 mm pitch, 17 × 17 matrix, 14 × 14 mm body, and 1.52 mm maximum height.
  • A STEP 3D model is present.
Mismatches / deficiencies
  1. Package or Case Code is set to TO. This is incorrect. The ordering-code package field is VM, meaning 289-pin MAPBGA, 14 × 14 mm, 0.8 mm pitch. TO normally denotes transistor-outline packaging and is not applicable.
  2. The project description says “Microprocessor”, while NXP markets the i.MX RT1173 as a crossover MCU. This is not a pinout error, but “microcontroller/crossover MCU” is more precise.
  3. No explicit NXP product-page URL is stored, although the official page exists at https://www.nxp.com/part/MIMXRT1173CVM8A.
  4. Lifecycle/status information returned by indexed metadata included “Not for New Designs”; this should be confirmed directly on the current NXP product page before using it as a sourcing decision.
Schematic symbol and terminal review
  • The project contains 289 terminal entries, matching the package ball count.
  • Terminal names cover the expected GPIO banks, supplies, grounds, DCDC pins, reset/control, clocks, USB, MIPI CSI/DSI, analog and reference pins.
  • Sampled and datasheet-queried mappings agree with NXP Tables 115–117, including GPIO_EMC_B1_10=A2, GPIO_SD_B1_03=B17, USB1_DN=E16, USB1_DP=E17, POR_B=T10, XTALI=U16, XTALO=T16, CLK1_N=T15, CLK1_P=U15, and the MIPI pairs.
  • Repeated supply/ground names use numeric suffixes such as VSS_22, NVCC_EMC1_2, and VDD_SOC_IN_6. This is acceptable for unique terminal designators, but the Pin Description should retain the unsuffixed NXP signal name and ball-specific context.
Symbol deficiencies
All observed terminals have Pin Type = Unspecified and no populated Pin Description, Pin Group, Section, Terminal Order, or Pin Orientation properties. The custom symbol does have explicit Symbol Pin Position coordinates, but the missing semantic metadata materially reduces ERC quality and usability.
Priority corrections:
  • Classify all supply inputs and grounds correctly.
  • Classify outputs such as PMIC_ON_REQ and PMIC_STBY_REQ as outputs.
  • Classify reset, wake, test, VBUS and clock pins appropriately.
  • Add descriptions from Tables 115–116, including power domain, default function/mode, default pull state and nominal voltage where applicable.
  • Organize terminals into broad functional groups: Power, Ground, DCDC/PMU, Reset/Boot/Control, Clocks, USB, MIPI CSI, MIPI DSI, Analog, GPIO AD, GPIO EMC1, GPIO EMC2, GPIO DISP1, GPIO DISP2, GPIO SD1, GPIO SD2, GPIO LPSR and GPIO SNVS.
Pin-map confidence
No wrong signal-to-ball mapping was found in the retrieved mappings. However, the available inspection response was truncated when returning all 289 terminal property records, so this review cannot claim a machine-complete 289-row equality proof. A full exported terminal table compared row-by-row with NXP Tables 115–117 is recommended before publishing the part.
Footprint review
Nominal structure
  • 289 pads and one footprint are present.
  • Pad names correspond to terminal signal names.
  • The footprint asset name is nominally consistent with the official 17 × 17, 0.8 mm-pitch, 14 × 14 mm MAPBGA.
  • Circular SMD pads are used.
  • A 3D model node is present.
Critical footprint mismatch
The computed PCB geometry is approximately 1000× too small:
  • A sampled outer-ball coordinate is reported as about 0.0064 mm from center, but a 17 × 17 array at 0.8 mm pitch requires 6.4 mm from center.
  • Sampled pad size is reported as 0.000394 mm, while the encoded/imported land size appears intended to be approximately 0.394 mm.
This strongly indicates a meter-to-millimeter import/scale error. In its current computed form, the footprint is not manufacturable and will not match the physical package. The footprint and 3D model should be checked together for the same 1000× scaling issue.
Other footprint verification gaps
  • Pin-A1 silkscreen/fabrication marking was not confirmed. The NXP drawing explicitly identifies an A1 index area.
  • Courtyard and assembly/fabrication outlines were not confirmed; imported fab shapes appear disabled in the current rule set.
  • Solder-mask expansion and paste-aperture settings were not explicitly visible. They should be verified against the PCB fabricator’s BGA process and NXP land-pattern guidance rather than inferred from package ball diameter.
  • The NXP package drawing is marked non-JEDEC and drawing 98ASA01216D / SOT1534-4, so final mechanical verification should use the official drawing.
Overall assessment
Part identity and nominal pin count/package selection are correct, and sampled pin mappings agree with the official datasheet. The part is not ready for reliable reuse because the footprint geometry appears 1000× underscaled, the package property is wrong (TO), and terminal descriptions/types/grouping are largely absent.
  1. Correct footprint units/scale and verify 0.8 mm pitch, ±6.4 mm outer-ball centers, intended land diameter, 14 × 14 mm body outline and A1 orientation.
  2. Change Package or Case Code from TO to VM or a descriptive 289-MAPBGA (14×14 mm, 0.8 mm pitch) value.
  3. Populate pin electrical types and descriptions from NXP Tables 115–116.
  4. Add broad Pin Group/Section metadata and deterministic ordering.
  5. Perform a complete exported 289-row terminal-to-ball comparison and inspect the corrected footprint/STEP overlay before publishing.

  • Scope and sources

  • Part identity and key specifications

  • Metadata review

  • Correct

  • Mismatches / deficiencies

  • Schematic symbol and terminal review

  • Symbol deficiencies

  • Pin-map confidence

  • Footprint review

  • Nominal structure

  • Critical footprint mismatch

  • Other footprint verification gaps

  • Overall assessment

  • Recommended remediation order

Documents

Assets

MIMXRT1173CVM8A

BGA289C80P17X17_1400X1400X152.kicad_modFootprint

MIMXRT1173CVM8A

MIMXRT1173CVM8A Symbol.svgDefault
MIMXRT1173CVM8A

MIMXRT1173CVM8A

MIMXRT1173CVM8A.stp3D Model
MIMXRT1173CVM8A-thumb.png

MIMXRT1173CVM8A-thumb.png

MIMXRT1173CVM8A-thumbThumbnail

MIMXRT1173CVM8A

MIMXRT1173CVM8A thumbnail
Dual-Core Crossover MCU with Arm® Cortex®-M7 and Cortex®-M4 Cores – High-performance crossover microcontroller designed for industrial automation, edge AI, HMI, motor control, robotics, audio processing, IoT gateways, medical devices, and advanced embedded systems. The NXP MIMXRT1173CVM8A integrates an Arm® Cortex®-M7 core running up to 800 MHz and an Arm® Cortex®-M4 core running up to 400 MHz, delivering real-time performance without an external operating system. It features 2 MB on-chip SRAM with support for external program memory, making it suitable for graphics, audio, and complex control applications.
The device includes 20-channel 12-bit SAR ADCs, 12-bit DAC, 10/100 Ethernet, USB 2.0 OTG, CAN FD, SD/MMC, I²C, SPI, UART/USART, SAI, SPDIF, LCD interface, camera interface, PWM, DMA, watchdog timers, temperature sensor, and extensive external memory interfaces (SEMC/FlexSPI). It also provides Secure Boot, AES, SHA, TRNG, tamper detection, and other hardware security features for secure embedded applications. Operates from 1.65–1.95 V core and 3.0–3.6 V I/O supplies, over a −40°C to +105°C junction temperature range, and is housed in a 289-ball MAPBGA (14 × 14 mm) package. The MIMXRT1173CVM8A is currently Not Recommended for New Designs (NRND), with MIMXRT1173CVM8B listed as the recommended replacement.
#NXP #MIMXRT1173CVM8A #iMXRT1170 #CortexM7 #CortexM4 #DualCoreMCU #CrossoverMCU #IndustrialAutomation #EdgeAI #MotorControl #EmbeddedSystems

Properties

MIMXRT1173CVM8A

NXP

Microprocessor

nxp.com/docs/en/nxp/data-sheets/IMXRT1170IEC.pdf

IC

TO

parametric-v1

Pricing & Availability

DPN

Stock

Qty 1

3

0–137

$14.33–$21.3205

1

126

$23.77

3

137–9.9K

$13.4283–$21.3205

Controls