Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.
I’ll audit the part metadata, locate and verify the official NXP datasheet if needed, then compare the symbol pins and footprint geometry against the authoritative package and pin tables. I’ll update the Datasheet property and report any mismatches with evidence.
Review complete. The 144-pin symbol mapping and LQFP footprint are consistent with the NXP datasheet; no missing, extra, or misnumbered pins were found. The Datasheet URL was already populated, so it was not changed.
Key flags:
High: All 144 pins have Pin Type = Unspecified, limiting ERC.
Medium: Pin descriptions and an explicit package property are missing.
Info: NXP lists the A revision as not recommended for new designs; MIMXRT1024DAG5B is active.
Reviewed the current project metadata, all 144 schematic terminals, the complete footprint pad set, footprint outline, and attached 3D model against the NXP i.MX RT1024 consumer datasheet (IMXRT1024CEC, Rev. 2, 01/2022).
The Datasheet URL property was already populated, so no property mutation was required. Its current value is a Flux-hosted PDF rather than the public NXP URL.
Current part information
Table
Field
Current value
Result
Project / MPN
MIMXRT1024DAG5A
Pass — exact NXP orderable part
Manufacturer
NXP
Pass
Part Type
Microprocessors
Minor taxonomy issue — NXP markets RT1024 as a crossover MCU/processor; “Microcontroller” or “Crossover MCU” would be clearer
Designator Prefix
IC
Pass
Pin count
144
Pass
Datasheet URL
Flux-hosted uploaded PDF
Present; no update required by the request
Explicit Package property
Not found
Metadata omission
Project description
Detailed Cortex-M7 MCU description
Mostly consistent with the datasheet
Key specifications
Arm Cortex-M7 crossover MCU/processor, up to 500 MHz.
4 MB on-chip flash and 256 KB configurable on-chip RAM/TCM.
Consumer junction-temperature grade: 0 °C to +95 °C.
Plastic 144-pin LQFP, 20 × 20 mm body, 0.5 mm lead pitch.
Package overall lead span: 22 × 22 mm; maximum height 1.60 mm.
90 GPIOs.
10/100 Ethernet, USB 2.0 OTG with PHY, 2× CAN, 2× SD/eMMC, 8× UART, 4× I²C, 4× SPI, 3× SAI, SPDIF, timers/PWM, 2× ADC, and 4× ACMP.
The exact DAG5A ordering code denotes the 500 MHz consumer-grade 144-LQFP A-revision device.
NXP currently lists the A-revision orderable part as not recommended for new designs; the B-revision is the active alternative in the same package family.
Schematic symbol cross-check
Pin map
Exactly 144 terminals are present.
Pin numbers cover 1 through 144.
The terminal names and pin numbers match the NXP package contact assignment.
All eight NC contacts are present at pins 77, 87, 88, 89, 90, 91, 92, and 104.
Repeated supply and ground names are intentionally suffixed in Flux (VSS_1, VDD_SOC_IN_1, etc.); their physical pin numbers match the datasheet.
High — incomplete electrical semantics: every terminal currently has Pin Type = Unspecified. This weakens ERC because power, ground, input, output, bidirectional, analog, and NC behavior is not represented.
Medium — missing descriptions: no Pin Description property is populated. The terminal names are correct, but users do not get datasheet descriptions or signal behavior directly in the symbol.
Pass — organization: unlike the earlier audit, the current terminals do have populated Pin Group and Section values (Power, Ground, USB, Clock, System Control, EMC GPIO, SD GPIO, AD GPIO, Analog, and No Connect).
Footprint cross-check
Footprint asset: FP_QFP50P2200X2200X160-144N.
The asset identity encodes 0.50 mm pitch, 22 × 22 mm overall span, 1.60 mm maximum package height, and 144 leads — consistent with the NXP mechanical drawing.
The footprint has 144 perimeter pads and no exposed center pad, matching the package.
The current outline is 20 × 20 mm at ±10 mm, and the on-screen/current layout scale is consistent with a real 20 mm-body LQFP. The previously reported 1000× scale error is not present in the current revision.
Each schematic terminal has a corresponding named footprint pad; no missing or extra pad was found.
A MIMXRT1024DAG5A.stp 3D model is attached.
Footprint limitations of this audit
The available structured footprint view exposes the pad inventory and package outline but not every pad’s computed copper size and numeric pad field in the audit response. The package asset identity, count, visible scale, and terminal-to-pad inventory are consistent; no concrete footprint mismatch was found in the current revision.
Mismatch summary
Table
Severity
Area
Finding
High
Symbol
All 144 terminals use Pin Type = Unspecified, reducing ERC effectiveness
Medium
Symbol
Pin descriptions are absent
Medium
Metadata
Explicit package/case property is absent; expected value is 144-LQFP, 20 × 20 mm, 0.5 mm pitch (AG)
Low
Metadata
Microprocessors is defensible but less precise than crossover MCU/microcontroller
Info
Lifecycle
NXP lists MIMXRT1024DAG5A as not recommended for new designs; MIMXRT1024DAG5B is active
Pass
Pin map
144/144 pin names and numbers match the datasheet
Pass
Footprint
Correct package class, pad count, outline scale, and no exposed pad
Pass
Datasheet property
Already populated; no mutation required
Changes made
Updated this audit to reflect the current project revision.
No component property was changed because a Datasheet URL was already set.
No symbol or footprint corrections were applied; the findings above are review results only.