Part Datasheet Review
Update the pin types, add pin descriptions, rename NCS active-low, and adjust the side pads to 0.80 mm.
Thought for 8 sec
I’ll update the symbol terminal metadata, rename the chip-select pin to active-low notation, adjust the QBB side-pad land length to 0.80 mm, then re-inspect the part.
Worked for 2 mins 11 sec
Symbol metadata and active-low naming are updated; the 14 side pads have been resized to 0.80 mm. I’m verifying the final schematic and footprint now.
Worked for 3 mins 38 sec
Completed the requested cleanup: pin types/descriptions are set,
NCS is now ~CS, and all 14 side pads are now 0.80 mm long while EP remains unchanged.Open items:
- EP still needs board-level VSS connection guidance when used in a design.
- Thermal vias and segmented EP paste are still assembler/application dependent.
I also updated Part Information Review: MCP2518FDT-E/QBB with the applied changes.
Finalize and verify part
Run ERC/DRC
Verify footprint geometry
Add EP guidance
Prepare for publishing
Refine this doc
Ask about this doc
Part Information Review: MCP2518FDT-E/QBB
Date: 2026-07-09
Sources Reviewed
- Project part:
silicon-yard/mcp2518fdt-eqbb - Project MPN:
MCP2518FDT-E/QBB - Manufacturer: Microchip Technology
- Datasheet property after review: https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/External-CAN-FD-Controller-with-SPI-Interface-DS20006027B.pdf
- Prior Datasheet URL: Mouser-hosted Microchip DS20006027A PDF
- Datasheet used for extraction in Flux: Mouser-hosted Microchip DS20006027A text extraction, cross-checked against Microchip official DS20006027B web result
Project Metadata Review
Table
| Field | Project value | Datasheet / official source check | Status |
|---|---|---|---|
| Manufacturer Part Number | MCP2518FDT-E/QBB | Ordering example identifies MCP2518FDT-E/QBB as tape-and-reel, extended temperature, QBB VDFN | OK |
| Manufacturer | Microchip Technology | Microchip official product/datasheet source | OK |
| Description | CAN controller / CAN FD controller with SPI interface | Device is a stand-alone external CAN FD controller with SPI interface; it is not a CANH/CANL physical transceiver | OK, but wording should avoid implying a transceiver |
| Part Type | Integrated Circuits | Interface/controller IC | OK |
| Designator Prefix | IC | Integrated circuit convention | OK |
| Pin count / pads | 15 schematic terminals and 15 PCB pads | QBB is 14-lead VDFN plus exposed pad EP as terminal 15 | OK |
| Datasheet URL | Updated to Microchip DS20006027B official PDF | Current official manufacturer-hosted PDF found | Updated |
Key Datasheet Specs
Table
| Parameter | Value |
|---|---|
| Function | External CAN FD controller with SPI interface |
| CAN modes | Mixed CAN 2.0B and CAN FD mode; CAN 2.0B mode |
| Standards | ISO 11898-1:2015 CAN protocol controller; requires external CAN transceiver for CANH/CANL |
| Nominal/arbitration bit rate | Up to 1 Mbps |
| CAN FD data bit rate | Up to 8 Mbps |
| SPI clock | Up to 20 MHz; FSCK must be <= FSYSCLK/2 |
| VDD operating range | 2.7 V to 5.5 V |
Temperature grade for -E | -40 C to +125 C |
| High-temp family option | -H: -40 C to +150 C, not this exact MPN |
| Typical active current | 15 mA typical, 20 mA max at 40 MHz SYSCLK and 20 MHz SPI activity |
| Sleep current | 15 uA typical, 60 uA max at TAMB <= +85 C; up to 600 uA max at +150 C |
| Low-power mode current | 4 uA typical, 10 uA max |
| Absolute max VDD | -0.3 V to +6.0 V |
| I/O voltage absolute max | -0.3 V to VDD + 0.3 V |
| ESD | HBM +/-4 kV, MM +/-400 V, CDM +/-750 V |
| Package | QBB = 14-lead VDFN, 4.5 x 3.0 mm body, 1.6 x 4.2 mm exposed pad, stepped wettable flanks |
| Thermal resistance | DFN-14 thetaJA typ. 64.1 C/W |
Schematic Symbol Pin Cross-Check
Table
| Pin | Project terminal | Datasheet pin name | Datasheet type | Datasheet description | Status |
|---|---|---|---|---|---|
| 1 | TXCAN | TXCAN | O | Transmit output to CAN FD transceiver | OK; project Pin Type is Unspecified |
| 2 | RXCAN | RXCAN | I | Receive input from CAN FD transceiver | OK; project Pin Type is Unspecified |
| 3 | CLKO/SOF | CLKO/SOF | O | Clock output / Start-of-Frame output | OK; project Pin Type is Unspecified |
| 4 | ~INT | INT | O | Interrupt output, active low | Name uses Flux active-low notation; project Pin Type is Unspecified |
| 5 | OSC2 | OSC2 | O | External oscillator output | OK; project Pin Type is Unspecified |
| 6 | OSC1 | OSC1 | I | External oscillator input | OK; project Pin Type is Unspecified |
| 7 | VSS | VSS | P | Ground | OK; project Pin Type is Unspecified |
| 8 | INT1/GPIO1 | I/O | RX interrupt output, active low / GPIO | Name uses Flux active-low notation; project Pin Type is Unspecified | |
| 9 | INT0/GPIO0/XSTBY | I/O | TX interrupt output, active low / GPIO / transceiver standby output | Name uses Flux active-low notation; project Pin Type is Unspecified | |
| 10 | SCK | SCK | I | SPI clock input | OK; project Pin Type is Unspecified |
| 11 | SDI | SDI | I | SPI data input | OK; project Pin Type is Unspecified |
| 12 | SDO | SDO | O | SPI data output | OK; project Pin Type is Unspecified |
| 13 | NCS | nCS | I | SPI chip select input, active low | Functional match, but active-low notation is not explicit in project name |
| 14 | VDD | VDD | P | Positive supply | OK; project Pin Type is Unspecified |
| 15 | EP | EP | P | Exposed pad; connect to VSS | OK, but should be documented and typed as ground/power/passive |
Footprint Cross-Check
Project footprint asset:
SON65P300X450X90-15N-D.kicad_modTable
| Footprint feature | Project value | Datasheet / land pattern value | Status |
|---|---|---|---|
| Body outline | 3.0 x 4.5 mm | 3.0 x 4.5 mm QBB VDFN body | OK |
| Pad count | 14 side pads + EP pad = 15 | 14 leads + exposed pad | OK |
| Pin pitch | 0.65 mm | 0.65 mm BSC | OK |
| Side pad width | 0.35 mm | 0.35 mm recommended land width | OK |
| Side pad length | 0.85 mm effective land length | 0.80 mm recommended land length | Minor mismatch: +0.05 mm |
| Contact pad spacing C | 3.00 mm center-to-center side spacing inferred from +/-1.45 mm centers and pad geometry | 3.00 mm | OK / consistent |
| EP copper land | 1.70 x 4.25 mm | Recommended center pad 1.70 x 4.25 mm; package EP nominal 1.60 x 4.20 mm | OK |
| Pad-to-EP gap | Approx. 0.175 mm if 0.85 mm side pad land is used | 0.20 mm recommended G1/G2 | Minor mismatch driven by side pad length |
| Pin-1 marker / chamfer | Fab chamfer and silk pin-1 dot present | Pin-1 index required by package drawing | OK |
| Thermal vias | Not included in footprint | Land pattern gives 0.30 mm via diameter and 1.00 mm via pitch guidance | Not necessarily a footprint error; board-level implementation note |
| EP paste | Single full EP paste aperture implied by pad definition | Large EPs often use reduced/windowed paste per assembler practice | Manufacturing caution |
| 3D model | MCP2518FDT-E_QBB.stp present | Package model should match QBB orientation | Likely OK; visually verify pin-1 orientation if using 3D assembly checks |
Mismatches / Issues Flagged
- Pin types are all
Unspecified. Datasheet pin types should be applied so ERC and downstream users know which pins are inputs, outputs, power, ground, or bidirectional. - Pin descriptions are missing. Each terminal should carry the datasheet pin function text, especially EP = "Exposed pad; connect to VSS".
- Pin 13 active-low naming is ambiguous. Datasheet uses
nCS; project usesNCS. Consider renaming to~CS,~NCS, ornCSfor consistency with~INTnotation. - Footprint side pad length is slightly longer than the Microchip recommended land pattern. Current effective side land length appears to be 0.85 mm versus datasheet recommended 0.80 mm. This reduces the EP-to-side-pad gap from 0.20 mm to about 0.175 mm. The deviation is small but real.
- Exposed-pad assembly details are not captured. EP should be tied to VSS; if thermal performance matters, add tented/filled thermal vias per board design. Consider segmented/reduced paste aperture for assembly yield.
- Description should avoid implying an integrated CAN transceiver. MCP2518FD is a controller only; it still requires an external CAN transceiver for CANH/CANL.
- Datasheet source was updated. The old property pointed to a Mouser-hosted DS20006027A copy. The project now points to Microchip's official DS20006027B PDF.
Recommended Fixes
- Update terminal
Pin TypeandPin Descriptionproperties from the datasheet table. - Rename pin 13 from
NCSto an active-low form such as~CSornCS. - Decide whether to adjust the side pad land length from 0.85 mm to 0.80 mm to exactly match Microchip's recommended land pattern.
- Add implementation guidance that EP must connect to VSS, preferably to a ground plane.
- For board designs using this part, consider thermal vias under EP and segmented paste apertures based on assembler rules.
Update Applied: 2026-07-09
- Set all terminal
Pin Typevalues to datasheet-aligned Flux types. - Added
Pin Descriptiontext to all terminals. - Renamed pin 13 from
NCSto~CSto show active-low chip select. - Resized all 14 side pads to
0.80 mmland length; EP remains1.70 x 4.25 mm. - Remaining board-level guidance: EP should be connected to VSS; thermal vias and segmented paste remain application/assembler-dependent.
Sources Reviewed
Project Metadata Review
Key Datasheet Specs
Schematic Symbol Pin Cross-Check
Footprint Cross-Check
Mismatches / Issues Flagged
Recommended Fixes
Update Applied: 2026-07-09
