Pin groups, sections, and terminal ordering are absent
Thus the symbol does not identify Gate, Source, or Drain despite having the correct numeric pins. The rendered custom symbol is also a plain rectangular body rather than a recognizable N-MOSF symbol.
Footprint findings
Three rectangular SMD pads, logically associated with pins 1–3
Pad centers from footprint source:
1: (−1.062, −0.65) mm
2: (−1.062, +0.65) mm
3: (+1.062, 0) mm
Each pad: 0.500 × 0.525 mm, rotated 90°
Fabrication body outline: 1.6 × 2.0 mm
Courtyard: 2.95 × 2.30 mm
3D STEP model is present.
Datasheet package is approximately 2.1 × 2.0 × 0.85 mm, 0.65 mm pitch.
Datasheet land-pattern example specifies 0.4 × 0.6 mm lands. The stored 0.500 × 0.525 mm pads therefore do not match the recommended land geometry.
Flux pad labels display as ~; numbering is only recoverable through terminal UID association.
Mutation
Unattempted/not applicable: Datasheet update, because the property was already non-empty.
No symbol, footprint, or other properties were altered.
Safe to use as-is?
No. The numeric pin mapping appears recoverable and correct, but the unnamed/untyped symbol terminals create a substantial connection-error risk, and the footprint pad geometry differs from the official recommended land pattern. The part should be corrected and footprint-validated before production use.
The audit is complete: the datasheet was already present, and the main issues are unnamed/untyped symbol pins plus footprint lands that differ from onsemi’s recommendation. I’m recording the detailed findings now.
Audit complete. The datasheet was already populated, so it was not changed; metadata is broadly correct, but the symbol lacks Gate/Source/Drain names and types, and the footprint lands differ from onsemi’s recommendation. The part is not production-ready as-is, and I filed an internal quality report.
Single N-channel power MOSFET, 1.8 V gate-drive series
Drain-source voltage, VDSS
30 V
Gate-source voltage, VGSS
±12 V
Continuous drain current, ID
2 A
Limited-duration drain current
2.5 A, ≤10 s, ≤1% duty
Pulsed drain current
8 A, ≤10 µs, ≤1% duty
RDS(on), VGS = 4.5 V, ID = 1 A
125 mΩ typ, 165 mΩ max
RDS(on), VGS = 2.5 V, ID = 0.5 A
165 mΩ typ, 235 mΩ max
RDS(on), VGS = 1.8 V, ID = 0.3 A
250 mΩ typ, 375 mΩ max
Gate threshold / cutoff voltage
0.4–1.3 V at VDS = 10 V, ID = 1 mA
Power dissipation
0.8 W DC; 1.2 W for 10 s on specified ceramic substrate
Maximum channel temperature
150 °C
Storage temperature
−55 to +150 °C
Pin 1
Gate
Pin 2
Source
Pin 3
Drain
Thermal capability is strongly dependent on the specified 900 mm² × 0.8 mm ceramic test substrate. No explicit junction-to-ambient thermal resistance was identified in the audited datasheet information.
Schematic symbol cross-check
The symbol contains numeric pins 1, 2, and 3, but all three are named ~, typed Unspecified, and have no descriptions. Functional groups, sections, and terminal ordering are also absent.
Mismatch
Table
Pin
Datasheet function
Current symbol name/type
1
Gate
~ / Unspecified
2
Source
~ / Unspecified
3
Drain
~ / Unspecified
The custom symbol is a plain rectangular body rather than a recognizable N-channel MOSFET symbol. Although the pin numbers exist, the missing functional names and electrical types create a significant wiring-error risk.
Footprint cross-check
Three rectangular SMD pads are present and associated with pins 1–3.
Pad centers: pin 1 at (−1.062, −0.65) mm; pin 2 at (−1.062, +0.65) mm; pin 3 at (+1.062, 0) mm.
Stored pad size: 0.500 × 0.525 mm, rotated 90°.
Fabrication body outline: 1.6 × 2.0 mm.
Courtyard: 2.95 × 2.30 mm.
A STEP model is present.
Datasheet package dimensions are approximately 2.1 × 2.0 × 0.85 mm, with 0.65 mm pitch.
The official land-pattern example specifies approximately 0.4 × 0.6 mm lands.
Mismatch
The stored 0.500 × 0.525 mm pads do not match the official 0.4 × 0.6 mm recommended land dimensions. Pad numbering also renders as ~ in Flux and is only recoverable from terminal UID association, reducing reviewability.
Conclusion
The part should not be treated as production-ready as-is. The MPN, manufacturer, pin count, broad package class, and numeric pin mapping are consistent with the datasheet. However, the symbol lacks Gate/Source/Drain names, descriptions, and electrical types, and the footprint pad geometry differs from onsemi’s recommended land pattern. Correct and revalidate the symbol and footprint before production use.
N-Channel Power MOSFET – 30 V N-channel enhancement-mode MOSFET optimized for load switching, DC-DC converters, battery-powered devices, power management, motor control, and embedded switching applications. Features a 30 V drain-to-source voltage (VDS), 2 A continuous drain current, and 165 mΩ maximum RDS(on) at VGS = 4.5 V, with 1.8 V logic-level gate drive compatibility for low-voltage microcontroller interfaces. Offers 1.7 nC typical gate charge, 130 pF typical input capacitance, ultra-fast switching performance, and an integrated body diode for efficient power conversion. Rated for ±12 V gate-to-source voltage, 800 mW power dissipation, 150°C maximum junction temperature, and housed in a 3-pin MCPH3 (SC-70 / SOT-323) surface-mount package. This device is obsolete / not recommended for new designs.