TI MCF8329A1 Audit

C

cherepanyadima

Check this schematic component against the datasheet for [MPN] and assign the correct pin orientation, section, and terminal order without changing, replacing, renumbering, or remapping any pins. Remove the Pin Group property from all pins if it exists. Place Power pins first and Ground pins last. Within each section, distribute the pins as evenly as possible between the left and right sides; for example, split 10 pins as 5/5 and 11 pins as 5/6 or 6/5. If a section contains only one pin, leave it on the most appropriate side. Keep the symbol compact, balanced, and visually symmetrical. If a pin function is unclear, assign Unclear / Check datasheet, then apply all changes directly to the schematic component.

flux

I’ll incorporate that into the audit: using the verified MCF8329A1IREER pin table, I’ll assign section, orientation, and terminal order to every existing pin, remove all Pin Group properties, and preserve every pin number and mapping.

flux

The symbol organization and datasheet-backed metadata are applied. I’m doing the final readback now to confirm all 37 pins, ordering, types, descriptions, and footprint mappings remained intact.

flux

Updated the part to the official TI MCF8329A1IREER metadata and datasheet, with WQFN REE0036A, 36 pins plus exposed pad, 4.5–60 V operation, and −40°C to 125°C rating. All 37 terminals now have datasheet-verified types/descriptions, balanced sections and orientations, unique Power-first/Ground-last ordering, and no Pin Group properties; pin numbers and footprint mappings were preserved.
The footprint’s 5 × 4 mm body, 0.4 mm pitch, and exposed pad match the TI package drawing. Corrected mismatches included the incomplete MPN/description, missing datasheet and pin metadata, SCL’s type, and the SHA/SHB/SHC I/O classifications.
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Pins

Symbol

Layout

3D View

GVDD
Pin Number
8
PVDD
Pin Number
5
DVDD
Pin Number
36
AVDD
Pin Number
26
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
DGND
1
Ground
Ground
Left
34
Device digital ground
VREG
2
Power In
Power
Left
1
Internal DVDD regulator input
GCTRL
3
Output
Control and Interface
Right
25
External regulator gate control
GND
4
Ground
Ground
Right
36
Device power ground
PVDD
5
Power In
Power
Left
2
Gate-driver power supply input
CPL
6
Power Out
Power
Right
6
Charge-pump low switching node
CPH
7
Power Out
Power
Right
5
Charge-pump high switching node
GVDD
8
Power Out
Power
Right
7
Gate-driver power supply output
BSTA
9
Output
Gate Drive
Left
9
Phase A bootstrap output
SHA
10
Bi-Directional
Gate Drive
Left
10
Phase A high-side source, VDS monitor input, and gate-driver sink return
GHA
11
Output
Gate Drive
Left
11
Phase A high-side gate output
GLA
12
Output
Gate Drive
Left
12
Phase A low-side gate output
BSTB
13
Output
Gate Drive
Left
13
Phase B bootstrap output
SHB
14
Bi-Directional
Gate Drive
Left
14
Phase B high-side source, VDS monitor input, and gate-driver sink return
GHB
15
Output
Gate Drive
Right
15
Phase B high-side gate output
GLB
16
Output
Gate Drive
Right
16
Phase B low-side gate output
BSTC
17
Output
Gate Drive
Right
17
Phase C bootstrap output
SHC
18
Bi-Directional
Gate Drive
Right
18
Phase C high-side source, VDS monitor input, and gate-driver sink return
GHC
19
Output
Gate Drive
Right
19
Phase C high-side gate output
GLC
20
Output
Gate Drive
Right
20
Phase C low-side gate output
LSS
21
Power In
Power
Right
8
Low-side source and sense
SP
22
Input
Sense and Status
Left
29
Current-shunt amplifier positive input
SN
23
Input
Sense and Status
Left
30
Current-shunt amplifier negative input

MCF8329AREE